MFRC531集成电路：13.56MHz无接触通信解决方案

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"MFRC531是一款高度集成的13.56MHz非接触式通信读卡器集成电路，支持多种通信协议，包括MIFARE系列。" MFRC531集成电路是专为非接触式通信设计的一款先进芯片，其功能和电气特性在数据表中得到了详尽的阐述。该芯片旨在提供高效能的调制和解调功能，适用于被动式的非接触式通信场景。MFRC531家族的特点包括卓越的通信性能、广泛的支持协议、紧凑的全集成封装，以及与MFRC500、MFRC530和SLRC400的引脚兼容性，这使得它在设计时具有良好的兼容性和灵活性。 MFRC531支持所有MIFARE产品系列的识别协议，包括MIFARE Mini、MIFARE 1K、MIFARE 4K、MIFARE Ultralight、MIFARE DESFire EV1和MIFARE Plus。在数据表中，这些产品和协议统称为MIFARE，以简化阅读。这种广泛的协议支持使得MFRC531能够适应各种非接触式智能卡应用，如交通票务、门禁控制、支付系统等。在技术规格方面，MFRC531遵循ISO/IEC14443A和ISO/IEC14443B通信标准的全部协议层。这意味着它可以处理这两种标准下定义的各种操作和安全机制。然而，实现这些标准可能需要额外的组件，例如操作系统和其他硬件辅助模块，以完成完整的读写器系统。此外，MFRC531还具备一定的灵活性，可以适应不断变化的市场需求和技术发展。其设计考虑了系统和硬件层面的集成，提供了详细的指导，帮助工程师在实际项目中顺利地将该芯片纳入到他们的设计方案中。 MFRC531是一款强大的非接触式读卡器芯片，适用于各种需要高安全性和可靠性的非接触式通信应用。通过全面支持MIFARE协议和ISO/IEC14443标准，它为开发人员提供了设计高效、灵活的RFID系统的基石。在设计过程中，工程师可以利用MFRC531的数据表提供的详细信息，确保正确且有效地实现系统功能。

Product data sheet

PUBLIC

Rev. 3.4 — 26 January 2010

056634 16 of 116

NXP Semiconductors

MFRC531

ISO/IEC 14443 reader IC

9.2.2.3 Register initialization file (read/write)

The EEPROM memory content from block address 3 to 7 can initialize register sub

addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.4.1 on

page 86). This command requires the EEPROM starting byte address as a two byte

argument for the initialization procedure.

The byte assignment is shown in Table 16

The register initialization file is large enough to hold values for two initialization sets and

up to one block (16-byte) of user data.

Remark: The register initialization file can be read/written by users and these bytes can

be used to store other user data.

After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A

protocol.

9.2.3 Crypto1 keys (write only)

MIFARE security requires specific cryptographic keys to encrypt data stream

communication on the contactless interface. These keys are called Crypto1 keys.

9.2.3.1 Key format

Keys stored in the EEPROM are written in a specific format. Each key byte must be split

into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).

Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This

format is a precondition for successful execution of the LoadKeyE2 (see Section 11.6.1 on

page 88) and LoadKey commands (see Section 11.6.2 on page 88).

Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is

shown in Figure 7

Example: The value for the key must be written to the EEPROM.

• If the key was: A0h A1h A2h A3h A4h A5h then:

• 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.

Table 16. Byte assignment for register initialization at startup

EEPROM byte address Register address Remark

EEPROM starting byte address 10h skipped

EEPROM + 1 starting byte address 11h copied

... … …

EEPROM + 31 starting byte address 2Fh copied

Fig 7. Key storage format

001aak64

0 (LSB)Master key byte

Master key bits

EEPROM byte

address

Example

k7 k6 k5 k4 k7 k6 k5 k4

5Ah

k3 k2 k1 k0 k3 k2 k1 k0

n + 1

F0h

k7 k6 k5 k4 k7 k6 k5 k4

n + 2

5Ah

k3 k2 k1 k0 k3 k2 k1 k0

n + 3

E1h

5 (MSB)

k7 k6 k5 k4 k7 k6 k5 k4

n + 10

5Ah

k3 k2 k1 k0 k3 k2 k1 k0

n + 11

A5h

Product data sheet

PUBLIC

Rev. 3.4 — 26 January 2010

056634 17 of 116

NXP Semiconductors

MFRC531

ISO/IEC 14443 reader IC

Remark: It is possible to load data for other key formats into the EEPROM key storage

location. However, it is not possible to validate card authentication with data which will

cause the LoadKeyE2 command (see Section 11.6.1 on page 88

) to fail.

9.2.3.2 Storage of keys in the EEPROM

The MFRC531 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No

memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every

byte of the dedicated memory area can be the start of a key.

Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for

example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM

block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.

Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32

different keys can be stored in the EEPROM.

Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh.

9.3 FIFO buffer

An 8 × 64 bit FIFO buffer is used in the MFRC531 to act as a parallel-to-parallel converter.

It buffers both the input and output data streams between the microprocessor and the

internal circuitry of the MFRC531. This makes it possible to manage data streams up to

64 bytes long without needing to take timing constraints into account.

9.3.1 Accessing the FIFO buffer

9.3.1.1 Access rules

The FIFO buffer input and output data bus is connected to the FIFOData register. Writing

to this register stores one byte in the FIFO buffer and increments the FIFO buffer write

pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO

buffer read pointer and increments the FIFO buffer read pointer. The distance between the

write and read pointer can be obtained by reading the FIFOLength register.

When the microprocessor starts a command, the MFRC531 can still access the FIFO

buffer while the command is running. Only one FIFO buffer has been implemented which

is used for input and output. Therefore, the microprocessor must ensure that there are no

inadvertent FIFO buffer accesses. Table 17

gives an overview of FIFO buffer access

during command processing.

Table 17. FIFO buffer access

Active

command

FIFO buffer Remark

μp Write μp Read

StartUp - -

Idle - -

Transmit yes -

Receive - yes

Transceive yes yes the microprocessor has to know the state of the

command (transmitting or receiving)

WriteE2 yes -

Product data sheet

PUBLIC

Rev. 3.4 — 26 January 2010

056634 19 of 116

NXP Semiconductors

MFRC531

ISO/IEC 14443 reader IC

9.3.4 FIFO buffer registers and flags

Table 17 shows the related FIFO buffer flags in alphabetic order.

9.4 Interrupt request system

The MFRC531 indicates interrupt events by setting the PrimaryStatus register bit IRq (see

Section 10.5.1.4 “

PrimaryStatus register” on page 49) and activating pin IRQ. The signal

on pin IRQ can be used to interrupt the microprocessor using its interrupt handling

capabilities ensuring efficient microprocessor software.

9.4.1 Interrupt sources overview

Table 19 shows the integrated interrupt flags, related source and setting condition. The

interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set

when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one

to the TReLoadValue[7:0] with bit TAutoRestart enabled.

Bit TxIRq indicates interrupts from different sources and is set as follows:

• the transmitter automatically sets the bit TxIRq interrupt when it is active and its state

changes from sending data to transmitting the end of frame pattern

• the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been

processed indicated by bit CRCReady = logic 1

• when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit

E2Ready = logic 1

The RxIRq flag bit indicates an interrupt when the end of the received data is detected.

The IdleIRq flag bit is set when a command finishes and the content of the Command

When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see

Section 9.3.3 on page 18

) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to

logic 1.

When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see

Section 9.3.3 on page 18

) and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to

logic 1.

Table 18. Associated FIFO buffer registers and flags

Flags Register name Bit Register address

FIFOLength[6:0] FIFOLength 6 to 0 04h

FIFOOvfl ErrorFlag 4 0Ah

FlushFIFO Control 0 09h

HiAlert PrimaryStatus 1 03h

HiAlertIEn InterruptEn 1 06h

HiAlertIRq InterruptRq 1 07h

LoAlert PrimaryStatus 0 03h

LoAlertIEn InterruptEn 0 06h

LoAlertIRq InterruptRq 0 07h

WaterLevel[5:0] FIFOLevel 5 to 0 29h

Product data sheet

PUBLIC

Rev. 3.4 — 26 January 2010

056634 20 of 116

NXP Semiconductors

MFRC531

ISO/IEC 14443 reader IC

9.4.2 Interrupt request handling

9.4.2.1 Controlling interrupts and getting their status

The MFRC531 informs the microprocessor about the interrupt request source by setting

the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as

source for an interrupt can be masked by the InterruptEn register interrupt enable bits.

If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending)

and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is

set to logic 1. Different interrupt sources can activate simultaneously because all interrupt

request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.

9.4.2.2 Accessing the interrupt registers

The interrupt request bits are automatically set by the MFRC531’s internal state

machines. In addition, the microprocessor can also set or clear the interrupt request bits

as required.

A special implementation of the InterruptRq and InterruptEn registers enables changing

an individual bit status without influencing any other bits. If an interrupt register is set to

logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. If a

specific interrupt flag is cleared, zero must be written to the SetIxx and the interrupt

If a content bit is not changed during the setting or clearing phase, zero must be written to

the specific bit location.

Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0

while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq

to logic 1 and leaves all other bits unchanged.

Table 19. Interrupt sources

Interrupt flag Interrupt source Trigger action

TimerIRq timer unit timer counts from 1 to 0

TxIRq transmitter a data stream, transmitted to the card, ends

CRC coprocessor all data from the FIFO buffer has been processed

EEPROM all data from the FIFO buffer has been

programmed

RxIRq receiver a data stream, received from the card, ends

IdleIRq Command register command execution finishes

HiAlertIRq FIFO buffer FIFO buffer is full

LoAlertIRq FIFO buffer FIFO buffer is empty

Table 20. Interrupt control registers

InterruptEn SetIEn reserved TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn

InterruptRq SetIRq reserved TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq

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