TI DS90UB947N-Q1: 1080p OpenLDI to FPD-LinkIII Serializer for Automotive Applications

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"TI-DS90UB947N-Q1.pdf 是一款FPD-Link串行器，用于视频和图像数据传输。该器件适用于汽车应用，符合AEC-Q100标准，能承受-40°C至+105°C的工作温度范围。它支持高达170MHz的时钟频率，可以处理WUXGA（1920x1200）和1080p60分辨率的图像，并具有24位色彩深度。" TI的DS90UB947N-Q1是一款FPD-Link III串行器，主要设计用于汽车行业的视频和图像处理应用。这款设备是AEC-Q100Grade 2认证的，这意味着它满足了汽车电子的严格可靠性要求，可以在宽温范围内稳定工作。在功能上，DS90UB947N-Q1能够处理高分辨率的视频流，如WUXGA（宽超高清，1920像素×1200像素）和1080p60（全高清，1920像素×1080像素，每秒60帧），并且支持24位色彩深度，确保了高质量的图像显示。该串行器支持双通道数据传输，每个通道的速率可达到3Gbps，总带宽高达6Gbps。其输入端口包括D0+/-到D7+/-，以及IDx和SPI控制的D_GPIO，这些接口用于接收来自图形处理器或LVDSDisplay的数据。输出端口则提供DOUT0+/-、DOUT1+/-等，将接收到的并行数据转换成串行信号，通过FPD-Link (OpenLDI) 接口传输到下游设备，如显示面板或其他解串器。 DS90UB947N-Q1还集成了时钟信号的输入/输出（CLK+//-, CLK2+//-），以同步数据传输。此外，设备提供了1.8V和3.3V的VDDIO电源选项，适应不同的接口电压需求。I2C接口允许对设备进行配置和控制，而1.2V的电源电压（VDDIO）用于确保低功耗操作。该器件的特性还包括SPI兼容的GPIO，可用于额外的系统控制和状态指示。同时，TI为产品提供了技术文档、软件工具和社区支持，方便用户进行设计、开发和故障排除。由于是生产数据，用户需要注意数据表末尾的重要通知，包括关于可用性、保修、安全关键应用的使用、知识产权事项和其他免责声明。 DS90UB947N-Q1是一款高性能、高可靠性的串行器，适合要求严苛的汽车视觉系统，如车载信息娱乐系统、驾驶辅助系统等，能有效处理高清视频流，确保图像质量和系统的稳定运行。

I2S_WC

I2S_D[A,B,C,D]

I2S_CLK

SCL

SDA

HD;STA

LOW

HD;DAT

HIGH

SU;DAT

SU;STA

SU;STO

START

REPEATED

START

STOP

HD;STA

START

BUF

DS90UB947N-Q1

www.ti.com

SNLS627 –DECEMBER 2019

Product Folder Links: DS90UB947N-Q1

Timing Diagrams (continued)

Figure 8. Serial Control Bus Timing Diagram

Figure 9. I2S Timing Diagram

6.10 Typical Characteristics

Figure 10. Serializer Output at 2.975 Gbps (85-MHz

OpenLDI Clock)

Figure 11. Serializer Output at 3.36 Gbps (96-MHz OpenLDI

Clock)

I2C

Interface

I2C

PAT

GEN

Open-LDI

OLDI

Interface

Open LDI

Analog

Regs

Clocks

DFT

Audio

I2S

FPD3 TX

Analog

FPD-Link III

FPD3 TX

Analog

FPD-Link III

FPD-Link III TX

Digital

FPD-Link III TX

Digital

FPD3

Output

Select

Config

Single/Dual

Control

DS90UB947N-Q1

SNLS627 –DECEMBER 2019

www.ti.com

Product Folder Links: DS90UB947N-Q1

7 Detailed Description

7.1 Overview

The DS90UB947N-Q1 converts a single or dual FPD-Link (Open LDI) interface (up to 8 LVDS lanes + 1 clock) to

an FPD-Link III interface. This device transmits a 35-bit symbol over a single serial pair operating up to 3.36-

Gbps line rate, or two serial pairs operating up to 2.975-Gbps line rate. The serial stream contains an embedded

clock, video control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal

quality and support AC coupling.

The DS90UB947N-Q1 serializer is intended for use with a DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB940-

Q1, or DS90UB948-Q1 deserializer.

The DS90UB947N-Q1 serializer and companion deserializer incorporate an I

C-compatible interface. The I

C-

compatible interface allows programming of serializer or deserializer devices from a local host controller. In

addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between a

serializer and deserializer, as well as remote I

C slave devices.

The bidirectional control channel (BCC) is implemented through embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial

link from one I

C bus to another. The implementation allows for arbitration with other I

C-compatible masters at

either side of the serial link.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 High-Speed Forward Channel Data Transfer

The High-Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, I2C,

GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 12 shows the serial stream per clock

cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,

balanced, and scrambled.

Figure 12. FPD-Link III Serial Stream

DS90UB947N-Q1

www.ti.com

SNLS627 –DECEMBER 2019

Product Folder Links: DS90UB947N-Q1

Feature Description (continued)

The device supports OpenLDI clocks in the range of 25 MHz to 96 MHz over one lane, or 50 MHz to 170 MHz

over two lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum), or 2.975 Gbps

maximum per lane (875 Mbps minimum) when transmitting over both lanes.

7.3.2 Back Channel Data Transfer

The Backward Channel provides bidirectional communication between the display and host processor. The

information is carried from the deserializer to the serializer as serial frames. The back channel control data is

transferred over both serial links along with the high-speed forward data, DC balance coding, and embedded

clock information. This architecture provides a backward path across the serial link together with a high-speed

forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information with line rate

of 5, 10, or 20 Mbps (configured by the compatible deserializer).

7.3.3 FPD-Link III Port Register Access

The DS90UB947N-Q1 contains two downstream ports, therefore some registers must be duplicated to allow

control and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two

sets of registers. Registers that are shared between ports (not duplicated) will be available independent of the

settings in the TX_PORT_SEL register.

Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both

bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing

simultaneous writes to both ports if both select bits are set.

Setting the PORT1_I2C_EN bit will enable a second I

C slave address, allowing access to the second port

registers through the second I

C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be

ignored.

7.3.4 OpenLDI Input Frame and Color Bit Mapping Select

The DS90UB947N-Q1 can be configured to accept 24-bit color (8-bit RGB) with two different mapping schemes,

shown in Figure 13 and Figure 14. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock

input to CLK± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock

periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL strap option or

by register (Table 11).

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