高性能开源FPGA SATA2接口设计与实现

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"本文介绍了一个高性能、开源的基于FPGA的SATA2核心设计与实现。该核心允许直接与硬件核心交互，适用于高性能和嵌入式计算应用。此外，它还具备总线接口和DMA引擎，可通过Linux块设备驱动程序使操作系统能够访问。实测结果显示，基于FPGA的实现能接近固态硬盘的理论峰值性能。核心支持原生命令队列，对于小块传输，尤其是在SSD中，性能提升显著。该SATA核心在Virtex-6 FPGA上仅占用1.5%的逻辑资源，具有高效的空间利用率。" **关键词解释** 1. **SATA2**: SATA（Serial Advanced Technology Attachment）是一种用于连接存储设备（如硬盘、光驱）到计算机主板的高速接口标准，SATA2是其第二代版本，提供更高的数据传输速率。 2. **FPGA**: Field-Programmable Gate Array，现场可编程门阵列，是一种半导体设备，可以被用户根据需求配置成各种数字逻辑电路。在本案例中，FPGA被用作实现SATA2接口的核心。 3. **直接硬件接口**: 直接与硬件核心交互意味着SATA2核心可以直接控制存储设备，减少了通过软件层的通信延迟，提高了性能。 4. **总线接口**: 用于连接核心与系统其余部分的通信路径，使得数据能在不同组件之间有效传输。 5. **DMA (Direct Memory Access)**: 直接内存访问，允许外围设备直接读取或写入系统内存，而无需CPU的介入，从而提高数据传输速度。 6. **Linux块设备驱动**: 一种操作系统内核组件，负责与硬件设备（如磁盘）进行交互，将底层硬件操作转换为操作系统可理解的抽象。 7. **固态硬盘(SSD)**: 使用闪存作为存储介质的高速存储设备，相比传统机械硬盘，SSD具有更快的读写速度和更低的延迟。 8. **原生命令队列(Native Command Queuing, NCQ)**: SATA接口的一项技术，允许硬盘优化命令执行顺序，减少等待时间，提高多任务处理时的性能。 9. **性能测试**: 使用固态硬盘进行的性能测试显示，FPGA实现的SATA2核心接近理论上的最大传输速率，证明了其高性能特性。 10. **资源利用率**: SATA核心在Virtex-6 FPGA上占用资源少，表明设计高效且节省空间，有利于在有限的硬件资源下实现更多功能。这个开源SATA2核心设计为高性能和嵌入式系统提供了强大的存储接口解决方案，通过FPGA实现了高效的硬件交互，并通过Linux驱动程序与操作系统兼容。原生命令队列的集成进一步提升了SSD的性能，特别是在处理小块数据时。同时，其小巧的逻辑资源占用展示了良好的硬件资源管理。

A HIGH PERFORMANCE, OPEN SOURCE SATA2 CORE

Ashwin A. Mendon, Bin Huang, and Ron Sass

Reconﬁgurable Computing Systems Lab

University of North Carolina at Charlotte

Charlotte, NC, USA

email: {aamendon,bhuang2,rsass}@uncc.edu

ABSTRACT

This paper describes the design and implementation of an

open source FPGA-based SATA2 core. It provides the abil-

ity to directly interface with hardware cores which is ben-

eﬁcial for high performance and embedded computing ap-

plications. Additionally, the core has a bus interface and

DMA engine that makes it available to the operating sys-

tem through a Linux block device driver. Measurements

with solid state drives reveal that our FPGA-based imple-

mentation achieves performance close to the disks’ theoret-

ical peak. In contrast, we ﬁnd that software overhead on

a modern Linux server prevents exploiting the full poten-

tial of these high speed storage devices. Native Command

Queueing is supported by the core and the performance re-

sults highlight its importance in the context of SSDs, espe-

cially for small block transfers. The small size of our SATA

core (1.5% of the logic resources on a Virtex-6 FPGA) indi-

cates that an on-chip RAID storage system is feasible.

1. INTRODUCTION

The introduction of high speed transceivers that can be con-

ﬁgured to be electrically compatible with industry standards,

such as SATA and SATA2, has enabled FPGAs to commu-

nicate with large, non-volatile storage devices. However,

commercial SATA cores have two shortcomings. First, they

are very expensive and, second, the cores are designed to

be accessed only from software. This may be sensible for

the simplest, most straight-forward System-on-a-Chip type

designs, but it limits the capabilities of directly interfacing

with FPGA-based cores.

This paper describes the design, implementation, and

performance measurements of an open source SATA2 core.

As coded, the SATA core can be used as the basis of a tra-

ditional “SATA chipset” for an operating system or used in

an unconventional way, such as the interface between an-

other hardware core and a non-volatile storage. This pro-

vides FPGA-based accelerators the ability to directly access

raw data from non-volatile storage. It also supports the abil-

ity to create FPGA-based ﬁlesystems in hardware [1,2]. The

latter is extremely important as non-volatile storage speed

and latencies are changing dramatically (ﬂash-based designs

today and phase-change memory in the future) while the

software stack and microprocessor frequency are not. Be-

yond demonstrating the functionality of the core, this paper

quantiﬁes the software overhead and demonstrates that this

penalty is substantial with current solid state drives. The

implementation also reveals that Native Command Queing

— which was developed to allow Winchester-style disks to

reorder outstanding requests — is also important to solid-

state drives, especially for small block transfers. Along with

the hardware core, which is available from OpenCores [3],

there is also an Open Source Linux block device driver ker-

nel module that makes the core available to the operating

system. Presently, the design supports the transceivers found

on Xilinx Virtex 5 and Virtex 6 parts.

The rest of the paper is organized as follows. In the

next section, the relevant aspects of the SATA standard are

explained along with related work. The design goals and

implementation details are presented in Section 3. In Sec-

tion 4, the performance of the core with multiple commodity

off-the-shelf drives (Winchester and Solid-State Drives) are

analyzed. This performance is compared to a commercial

SATA II host bus adaptor in a traditional microprocessor-

based system as well.

2. BACKGROUND

2.1. SATA Protocol

The SATA protocol is a computer bus standard for transfer-

ring data between a Host Bus Adapter (HBA) chipset and

a mass storage device [4]. SATA Gen 1 has a transmission

speed of 150 MB/s, which was increased to 300 MB/s in

SATA Gen 2. (The SATA Gen 3 speciﬁcation is available

and supports speeds upto 600 MB/s. However, we do not

have access to FPGA devices compatible with SATA Gen 3

yet.) Serial ATA was designed to overcome a number of lim-

itations of parallel ATA. The improvements include a four-

wire point-to-point high-speed serial interface that supports

978-1-4673-2256-0/12/$31.00

2012 IEEE 421

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