TL/F/5297
MM54HC08/MM74HC08 Quad 2-Input AND Gate
January 1988
MM54HC08/MM74HC08
Quad 2-Input AND Gate
General Description
These AND gates utilize advanced silicon-gate CMOS tech-
nology to achieve operating speeds similar to LS-TTL gates
with the low power consumption of standard CMOS inte-
grated circuits. The HC08 has buffered outputs, providing
high noise immunity and the ability to drive 10 LS-TTL loads.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
Y
Typical propagation delay: 7 ns (t
PHL
), 12 ns (t
PLH
)
Y
Fanout of 10 LS-TTL loads
Y
Quiescent power consumption: 2 mA maximum at room
temperature
Y
Low input current: 1 mA maximum
Connection Diagram
Dual-In-Line Package
TL/F/5297–1
Top View
Order Number MM54HC08 or MM74HC08
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.