JESD84-A441: e•MMC/CARD 4.41标准详解

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"JESD84-A441是JEDEC固态技术协会发布的一份标准，专注于Embedded MultiMediaCard (e•MMC) 和e•MMC/Card产品，该标准详细定义了高容量版本，包括可靠写入、启动、睡眠模式、双数据速率、多分区支持、安全增强、后台操作和高优先级中断等功能。这份标准适用于2010年3月，并且是MMCA（Multi-Media Card Association）规范的4.41版。" 正文: e•MMC，全称Embedded MultiMediaCard，是一种集成化的存储解决方案，主要应用于移动设备如智能手机、平板电脑和数字电视等。JESD84-A441标准是JEDEC为了确保这些设备的存储性能和兼容性而制定的行业规范，它定义了e•MMC的硬件接口、协议、功能和行为，以便于制造商和消费者之间的互通性。该标准的4.41版引入了一些关键特性： 1. **可靠写入**: 这个特性保证了在写入数据时的稳定性和耐用性，防止数据丢失或损坏，这对于频繁读写操作的移动设备尤为重要。 2. **启动功能**: 支持设备快速启动，减少了开机时间，提升了用户体验。 3. **睡眠模式**: 设计有低功耗的睡眠模式，使得设备在待机时能有效节能，延长电池寿命。 4. **双数据速率 (DDR)**: 允许设备在两个时钟周期内处理两次数据传输，显著提高了数据传输速度，对于需要快速存取大量数据的应用非常有利。 5. **多分区支持**: 可以将存储空间划分为多个逻辑分区，便于管理不同类型的文件和应用，比如系统分区、用户数据分区等。 6. **安全增强**: 提供了更高级别的数据保护机制，包括加密和访问控制，保护用户隐私和数据安全。 7. **后台操作和高优先级中断**: 允许在执行其他任务的同时进行数据处理，例如在下载文件时接听电话，而不会中断下载。高优先级中断确保关键任务可以优先处理。这份标准的制定旨在促进标准化，消除制造商和购买者之间的沟通障碍，确保不同厂商的e•MMC产品能够互换并提供一致的性能。同时，它也为购买者提供了选择和获取合适产品的依据，无论是国内还是国际使用。 JESD84-A441是e•MMC/CARD产品设计和开发的重要参考，它推动了移动设备存储技术的发展，提升了设备性能，优化了用户体验。随着技术的进步，后续的版本可能还会增加更多新的功能和改进，以满足不断变化的市场需求。

JEDEC Standard No. 84-A441

-xii-

Embedded MultiMediaCard(e•MMC) e•MMC/Card Product Standard, High Capacity,

including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports,

Security Enhancement, Background Operation and High Priority Interrupt (MMCA, 4.41)

CONTENTS(continued)

Page

Figure 43 — Stop transmission after last data block; card is busy programming ................................ 107

Figure 44 — Stop transmission after last data block; card becomes busy............................................ 107

Figure 45 — Bus test procedure timing ................................................................................................ 108

Figure 46 — Boot operation, termination between consecutive data blocks........................................ 108

Figure 47 — Boot operation, termination during transfer .................................................................... 109

Figure 48 — Bus mode change timing (push-pull to open-drain) ........................................................ 109

Figure 49 — Alternative boot operation, termination between consecutive data blocks...................... 110

Figure 50 — Alternative boot operation, termination during transfer .................................................. 110

Figure 51 — H/W reset waveform........................................................................................................ 112

Figure 52 — Noise filtering timing for H/W reset................................................................................ 112

Figure 53 — CRC7 generator/checker.................................................................................................. 158

Figure 54 — CRC16 generator/checker................................................................................................ 159

Figure 55 — Bus circuitry diagram....................................................................................................... 163

Figure 56 — Improper power supply.................................................................................................... 164

Figure 57 — Shortcut protection........................................................................................................... 164

Figure 58 — Power-up diagram............................................................................................................ 165

Figure 59 — e•MMC power-up diagram ..............................................................................................167

Figure 60 — The e•MMC power cycle................................................................................................. 168

Figure 61 — MultiMediaCard bus driver ............................................................................................. 170

Figure 62 — e•MMC internal power diagram ...................................................................................... 172

Figure 63 — Bus signal levels .............................................................................................................. 174

Figure 64 — Timing diagram: data input/output .................................................................................. 176

Figure 65 — Timing diagram: data input/output in dual data rate mode.............................................. 179

Figure A.1 — Power supply decoupling................................................................................................. 185

Figure A.2 — Modified MultiMediaCard connector for hot insertion ................................................... 186

Figure A.3 — Legend for command-sequence flow charts .................................................................... 189

Figure A.4 — SEND_OP_COND command flow chart ........................................................................ 190

Figure A.5 — CIM_SINGLE_CARD_ACQ .......................................................................................... 191

Figure A.6 — CIM_SETUP_CARD....................................................................................................... 192

Figure A.7 — CIM_STREAM_READ................................................................................................... 193

Figure A.8 — CIM_READ_BLOCK ..................................................................................................... 193

Figure A.9 — CIM_READ_MBLOCK.................................................................................................. 194

Figure A.10 — CIM_WRITE_MBLOCK ................................................................................................ 195

Figure A.11 — CIM_ERASE_GROUP.................................................................................................... 196

Figure A.12 — CIM_SECURE_ERASE..................................................................................................197

Figure A.13 — CIM_SECURE_TRIM..................................................................................................... 198

Figure A.14 — CIM_TRIM...................................................................................................................... 199

Figure A.15 — CIM_US_PWR_WP ........................................................................................................ 200

Figure A.16 — CIM_US_PERM_WP...................................................................................................... 201

Figure A.17 — Bus testing for eight data lines......................................................................................... 205

Figure A.18 — Bus testing for four data lines .......................................................................................... 205

Figure A.19 — Bus testing for one data line ............................................................................................ 205

Figure A.20 — Erase-unit size selection flow .......................................................................................... 207

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