XILINX FPGA AXI开发全面指南

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"XILINX FPGA AXI开发参考文档" Xilinx FPGA AXI（Advanced eXtensible Interface）开发参考文档是针对基于Xilinx FPGA的系统设计者的重要参考资料，该文档通常会涵盖AXI协议的详细信息，以及如何在Xilinx FPGA平台上实现和优化AXI接口的设计。AXI是业界广泛采用的一种高性能、高带宽的片上互连协议，它允许不同的处理元素，如处理器、存储器和外设之间高效地交换数据。文档版本为UG761(v14.3)，发布于2012年11月15日，提供了对AXI协议的全面指南，包括基础概念、架构、时序、协议规范和设计实例。AXI协议有多种类型，例如AXI4、AXI4-Lite和AXI4-Stream，每种类型适用于不同的应用场景，如控制平面和数据平面通信。在该文档中，你可能会找到以下关键知识点： 1. **AXI协议概述**：AXI协议的核心特性，包括写和读事务的流程，总线宽度（数据通道和地址通道），以及仲裁机制。 2. **AXI组件**：包括主设备（Master）、从设备（Slave）、仲裁器（Arbiter）和桥接器（Bridge）等，它们如何协同工作以实现高效的通信。 3. **AXI接口信号**：详细说明了地址、数据、控制和响应信号的定义和使用，这些信号定义了AXI接口的电气特性。 4. **AXI4与AXI4-Lite的区别**：AXI4-Lite是AXI4的一个简化版本，主要用于轻量级控制信号传输，没有独立的写应答和读应答通道。 5. **AXI4-Stream**：用于无缓冲的数据流传输，常用于高速信号处理和DMA（直接内存访问）应用。 6. **设计实例**：文档可能包含具体的硬件描述语言（如VHDL或Verilog）代码示例，展示了如何在FPGA设计中集成和配置AXI接口。 7. **性能优化**：指导如何通过参数化、流水线设计和时序分析来提高AXI接口的性能。 8. **工具支持**：可能涵盖Xilinx的Vivado或其他设计工具如何支持AXI设计，包括IP核集成、仿真和验证。 9. **故障排查**：提供常见问题和解决方案，帮助开发者解决在实现AXI接口时遇到的问题。 10. **知识产权（IP）核**：Xilinx提供的预配置AXI IP核，如DMA控制器、AXI交叉开关等，以及如何将这些IP核集成到设计中。尽管Xilinx提供这些材料供选择和使用，但文档明确指出，所有信息都是“按原样”提供，不提供任何明示或暗示的保修，包括但不限于适销性、非侵权性和特定目的适用性的保修。同时，Xilinx对因使用这些材料而产生的任何损失或损害不承担法律责任。请注意，由于没有提供具体内容，以上解释是基于一般AXI开发文档的典型内容。在实际文档中，会有更详细的描述和技术细节。

AXI Reference Guide www.xilinx.com 14

UG761 (v14.3) November 15, 2012

AXI Development Support in Xilinx Design Tools

Figure 2-1 shows the EDK Processor Implementation tab with an AXI4 bus type selected.

Port Name Truncation

System Generator shortens the AXI4-Stream signal names to improve readability on the

block; this is cosmetic and the complete AXI4-Stream name is used in the netlist. The name

truncation is turned on by default; uncheck the Display shortened port names option in

the block parameter dialog box to see the full name.

Port Groupings

System Generator groups together and color-codes blocks of AXI4-Stream channel signals.

In the example illustrated in the following figure, the top-most input port, data_tready,

and the top two output ports, data_tvalid and data_tdata belong in the same

AXI4-Stream channel, as well as phase_tready, phase_tvalid, and phase_tdata.

System Generator gives signals that are not part of any AXI4-Stream channels the same

background color as the block; the rst signal, shown in Figure 2-2, page 15, is an example.

Figure 2-1: EDK Processor Interface Implementation Tab

AXI Reference Guide www.xilinx.com 17

UG761 (v14.3) November 15, 2012

Xilinx AXI Infrastructure IP

New HDL designs for AXI4, AXI4-Lite, and AXI4-Stream masters and slaves can reference AXI

IP HDL design templates provided in Xilinx Answer Record37856.

Check this answer record

periodically for updates or new templates.

Xilinx AXI Infrastructure IP

Xilinx has migrated a significant portion of the available IP to AXI protocol. This section

provides an overview of the more complex IP that is used in many AXI-based systems.

The following common infrastructure Xilinx IP is available for Virtex

-6, Spartan

-6, and 7

series devices, and future device support:

• Xilinx AXI Interconnect Core IP

• Connecting AXI Interconnect Core Slaves and Masters

• External Masters and Slaves

• DataMover

• Xilinx AXI4-Stream Interconnect Core IP

• Centralized DMA

• Ethernet DMA

• Video DMA

• Memory Control IP and the Memory Interface Generator

Refer to Chapter 4, “Migrating to Xilinx AXI Protocols,” for more detailed usage information.

See the following for a list of all AXI IP:

http://www.xilinx.com/support/documentation/axi_ip_documentation.htm

Xilinx AXI Interconnect Core IP

The AXI Interconnect core IP (axi_interconnect) connects one or more AXI

memory-mapped master devices to one or more memory-mapped slave devices. The AXI

interfaces conform to the AMBA

AXI version 4 specification from ARM

, including the

AXI4-Lite control register interface subset.

Note:

The AXI Interconnect core IP is intended for memory-mapped transfers only; AXI4-Stream

transfers are not applicable, but instead can use the AXI4-Stream Interconnect core IP

(axis_interconnect). IP with AXI4-Stream interfaces are generally connected to one another, to

DMA IP, or to the AXI4-Stream Interconnect IP.

The AXI Interconnect core IP is provided as a non-encrypted, non-licensed (free) pcore in

the Xilinx Embedded Development Toolkit (EDK) and in the Project Navigator for use in

non-embedded designs using the CORE Generator

tool.

See the AXI_Interconnect IP (DS768)

[Ref 6]for more information.

AXI Reference Guide www.xilinx.com 18

UG761 (v14.3) November 15, 2012

Xilinx AXI Infrastructure IP

AXI Interconnect Core Features

The AXI Interconnect IP contains the following features:

• AXI protocol compliant (AXI3, AXI4, and AXI4-Lite), which includes:

Burst lengths up to 256 for incremental (INCR) bursts

Converts AXI4 bursts >16 beats when targeting AXI3 slave devices by splitting

transactions.

Generates REGION outputs for use by slave devices with multiple address decode

ranges

Propagates USER signals on each channel, if any; independent USER signal width per

channel (optional)

Propagates Quality of Service (QoS) signals, if any; not used by the AXI Interconnect

core (optional)

•Interface data widths:

AXI4: 32, 64, 128, 256, 512, or 1024 bits.

AXI4-Lite: 32 bits

• 32-bit address width

• The Slave Interface (SI) of the core can be configured to include 1-16 SI slots to accept

transactions from up to 16 connected master devices. The Master Interface (MI) can be

configured to comprise 1-16 MIT slots to issue transactions to up to 16 connected slave

devices.

• Connects 1-16 masters to 1-16 slaves:

When connecting one master to one slave, the AXI Interconnect core can optionally

perform address range checking. Also, it can perform any of the normal data-width,

clock-rate, or protocol conversions and pipelining.

When connecting one master to one slave and not performing any conversions or

address range checking, pathways through the AXI Interconnect core are

implemented as wires, with no resources, no delay and no latency.

Note:

When used in a non-embedded system such as CORE Generator, the AXI Interconnect core

connects multiple masters to one slave, which is typically a memory controller.

• Built-in data-width conversion:

Each master and slave connection can independently use data widths of 32, 64, 128,

256, 512, or 1024 bits wide:

- The internal crossbar can be configured to have a native data-width of 32, 64,

128, 256, 512, or 1024 bits.

- Data-width conversion is performed for each master and slave connection that

does not match the crossbar native data-width.

When converting to a wider interface (upsizing), data is packed (merged) optionally,

when permitted by address channel control signals (CACHE modifiable bit is

asserted).

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