STM32F103C8微控制器数据手册：中密度访问线，嵌入式ARM Cortex-M3

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"STM32F103C8是一款由STMicroelectronics生产的中密度访问线（Access Line）系列的32位微控制器，基于ARM Cortex-M3内核，具有64KB到128KB的闪存和10KB到16KB的SRAM。这款芯片适用于初学者学习，因其简单实用和清晰的特性描述而受到欢迎。" STM32F103C8是STM32家族中的一员，主要特点包括： 1. **高性能ARM Cortex-M3内核**：该处理器工作频率最高可达36MHz，提供1.25 DMIPS/MHz的性能，在0等待状态内存访问时。其单周期乘法和硬件除法功能增强了计算能力。 2. **存储器**：芯片内置64KB至128KB的闪存用于程序存储，以及10KB至16KB的SRAM作为高速数据存储。 3. **电源和复位管理**：支持2.0V至3.6V的应用电源和I/O，带有上电复位（POR）、掉电复位（PDR）和可编程电压检测器（PVD）。此外，芯片包含4至16MHz的晶体振荡器、8MHz工厂校准的内部RC振荡器和40kHz内部RC振荡器。 4. **时钟系统**：具有锁相环（PLL）功能，可以为CPU时钟提供更精确的频率，还支持一个32kHz的振荡器，用于实时时钟（RTC）并具有校准功能。 5. **低功耗模式**：包含睡眠、停止和待机模式，以及VBAT供电，以支持RTC和备份寄存器在低电源状态下运行。 6. **调试接口**：提供了串行线调试（SWD）和JTAG接口，便于开发过程中的程序调试。 7. **直接存储器访问（DMA）**：7通道的DMA控制器支持定时器、ADC、SPI、I2C和USART等外设的数据传输。 8. **模拟数字转换器（ADC）**：12位的ADC能在1微秒内完成转换，最多可支持16个通道，转换范围从0到3.3V。 9. **通信接口**：具备多个通信接口，包括定时器、ADC、SPI、I2C和USART，方便实现多种外设连接。 STM32F103C8是嵌入式开发中常用的微控制器之一，因其丰富的功能集和适中的价格，广泛应用于物联网设备、智能家居、工业控制和嵌入式系统设计等领域。其易用性和广泛的社区支持使得它成为初学者和专业开发者入门STM32系列的良好选择。

Description STM32F101x8, STM32F101xB

16/101 DocID13586 Rev 17

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected

to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 36 MHz. See

Figure 2 for details on the clock tree.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:

 Boot from User Flash

 Boot from System Memory

 Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

2.3.9 Power supply schemes

 V

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. 

Provided externally through V

pins.

 V

SSA

, V

DDA

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

and PLL (minimum voltage to be applied to V

DDA

is 2.4 V when the ADC is used).

DDA

and V

SSA

must be connected to V

and V

, respectively.

 V

BAT

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to Figure 11: Power supply scheme.

2.3.10 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

DocID13586 Rev 17 17/101

STM32F101x8, STM32F101xB Description

100

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

higher than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 10: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

 MR is used in the nominal regulation mode (Run)

 LPR is used in the Stop mode

 Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.3.12 Low-power modes

The STM32F101xx medium-density access line supports three low-power modes to achieve

the best compromise between low power consumption, short startup time and available

wakeup sources:

 Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

 Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode. 

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output or the RTC alarm.

 Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

Description STM32F101x8, STM32F101xB

18/101 DocID13586 Rev 17

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general purpose timers

TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit

registers used to store 20 bytes of user application data when V

power is not present.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512

Hz output to compensate for any natural crystal deviation. The RTC

features a 32-bit programmable counter for long term measurement using the Compare

default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.15 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to

reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

2.3.16 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

DocID13586 Rev 17 19/101

STM32F101x8, STM32F101xB Description

100

2.3.17 SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It

features:

 A 24-bit down counter

 Autoreload capability

 Maskable system interrupt generation when the counter reaches 0.

 Programmable clock source

2.3.18 General-purpose timers (TIMx)

There are three synchronizable general-purpose timers embedded in the STM32F101xx

medium-density access line devices. These timers are based on a 16-bit auto-reload

up/down counter, a 16-bit prescaler and feature 4 independent channels each for input

capture, output compare, PWM or one pulse mode output. This gives up to 12 input

captures / output compares / PWMs on the largest packages.



The general-purpose timers can work together via the Timer Link feature for synchronization

or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose

timers can be used to generate PWM outputs. They all have independent DMA request

generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

2.3.19 I

C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master

mode. A hardware CRC generation/verification is embedded.



They can be served by DMA and they support SM Bus 2.0/PM Bus.

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware

management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816

compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

2.3.21 Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-

duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

2.3.22 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

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