MediaTek MT7686：超低功耗Wi-Fi芯片详解

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"MT7686 datasheet" MT7686是MediaTek公司推出的一款高度集成的芯片，特别适合于低功耗应用。这款芯片集成了应用处理器、一个低功耗的单频1x1 802.11n Wi-Fi子系统以及电源管理单元（PMU）。MT7686基于ARM Cortex-M4浮点微控制器单元（MCU），内置4MB PSRAM和4MB闪存，确保了强大的处理能力。 MT7686支持多种接口，如UART（通用异步收发传输器）、I2C（集成电路间通信）、SPI（串行外围接口）、I2S（集成电路声音）、PWM（脉宽调制）、SDIO（安全数字输入输出）和ADC（模拟数字转换器）。这些丰富的接口使得该芯片能够与各种设备进行通信和数据交换。其Wi-Fi子系统包含了符合802.11b/g/n标准的无线射频、基带和MAC（媒体访问控制），旨在满足低功耗和高吞吐量应用的需求。此外，它还内嵌了一个32位RISC CPU（精简指令集计算机），能够完全卸载应用处理器的工作负载，从而降低主处理器的功耗并提高系统效率。 MT7686的数据手册特别指出，该文档包含MediaTek及其许可方的专有信息。只有在同意并受MediaTek的适用许可协议约束，并在许可协议中明确获得了使用权限的用户（称为“许可用户”）才能使用或复制此文档。非许可用户应立即停止对文档的任何访问或使用。未经授权的使用、复制或披露本文档将受到严格禁止。MediaTek对于与本文档或使用其内容有关的任何索赔概不负责，并且不提供任何形式的保证。文档中的规格可能会在不另行通知的情况下更改。文档版本为2.1，发布日期为2017年10月26日。这表明MT7686的技术参数和功能可能会随着更新而有所变动。MediaTek对本资料的提供仅基于“按原样”基础，不承担任何明示或暗示的保证。 MT7686是一款设计用于低功耗Wi-Fi应用的高效能芯片，适用于物联网(IoT)设备、智能家居产品以及其他需要高性能、低功耗无线连接的解决方案。其强大的处理能力和全面的接口选项使其成为许多智能设备的理想选择。

MediaTek MT7686 Datasheet

Page 10 of 53

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

1.3. System block diagram

EINT

PWM *6

UART *3

I2S *2

Wi-Fi system

Dynamic Clock Management

GPT

Timer 0

Timer 3

Timer 5

Timer 1

Timer 4

Timer 2AUXADC

SPI master

SPI slave

DMA

Pin MUX

Wi-Fi PSE

W-Fi single-

band RF

Wi-Fi MAC

DCXO

RTC

XOSC

32 kHz

XPLL

PLL1/PLL2

XTAL

32.768 kHz

XTAL

26/40 MHz

Crypto Engine

ARM® Cortex®-M4

192 MHz

FPU

NVIC

MPU

Cache

TCM

SPM

TRNG

SDIO master

SDIO slave

I2C *2

Wi-Fi

baseband

System Bus Matrix

SYSRAM

EMI

PSRAM

SFC

FLASH

Power

Management

Unit

3.3 V

Figure 1.3-1. MT7686 system block diagram

MediaTek MT7686 Datasheet

Page 11 of 53

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

2. Functional Overview

2.1. Host processor subsystem

2.1.1. ARM® Cortex®-M4 with FPU

The Cortex-M4 with FPU is a low-power processor with 3-stage pipeline Harvard architecture. It has reduced pin

count and low power consumption and delivers very high performance efficiency and low interrupt latency,

making it ideal for embedded microcontroller products.

The processor incorporates:

• IEEE754-compliant single-precision floating-point computation unit (FPU).

• A Nested Vectored Interrupt Controller (NVIC) to achieve low latency interrupt processing.

• Enhanced system debugging with extensive breakpoint.

• An optional Memory Protection Unit (MPU) to ensure platform security robustness.

The Cortex-M4 executes the Thumb®-2 instruction set with 32-bit architecture, with the high code density of 8-bit

and 16-bit microcontrollers. The instruction set is fully backward compatible with Cortex-M3/M0+.

MT7686 has further enhanced the Cortex-M4 with FPU to reduce the power by another 11% (in Dhrystone)

compared to the original Cortex-M4. Low power consumption is a significant feature for IoT and Wearables

application development.

2.1.2. Cache controller

A configurable 32KB cache is implemented to improve the code fetch performance when CPU accesses a non-zero

wait-state memory such as EMI, external flash or boot ROM through the on-chip bus.

The core cache is a small block of memory containing a copy of a small portion of cacheable data in the external

memory. If CPU reads a cacheable datum, the datum will be copied to the core cache. Once CPU requests the same

datum again, it can be obtained directly from the core cache (called cache hit) instead of fetching it again from the

external memory to achieve zero wait-state latency.

The cache can be disabled and this block of memory can be turned into tightly coupled memory (TCM), a high-

speed memory for normal data storage. The sizes of TCM and cache can be set to one of the following four

configurations:

• 32KB cache, 64KB TCM

• 16KB cache, 80KB TCM

• 8KB cache, 88KB TCM

• 0KB cache, 96KB TCM

2.1.3. Memory management

Three types of memories are implemented for use:

1) On-die memories (SRAMs) with up to 96KB at CPU clock speed with zero wait state.

MediaTek MT7686 Datasheet

Page 12 of 53

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

2) Embedded flash of 32Mbits to store programs and data.

3) Embedded pseudo SRAM (PSRAM) of 32Mbits for application storage.

The SRAMs are composed of TCMs and L1 caches. The L1 cache (up to 32KB) is implemented to improve processor

access performance of the long latency memories (flash and PSRAM).

TCMs are designed for high speed, low latency and low power demanding applications. Each TCM has its own

power state; active, retention or power-down. TCM must be in active state for normal read and write access.

Retention state saves the SRAM content and consumes the minimum leakage current with no access. Power-down

loses the content and consumes almost zero power.

The TCMs can also be accessed by other internal AHB masters like DMA or multimedia subsystem for low power

applications. These applications can run on TCM without powering on PSRAM or flash to save more power.

Boot ROM is also implemented for processor boot–up and its content is unchangeable.

2.1.4. Memory protection unit (MPU)

The MPU is an optional component to manage the CPU access to memory. The MPU provides full support for:

• Protection regions (up to 8 regions and can be further divided up into 8 sub-regions).

• Overlapping protection regions, with region priority.

• Access permissions.

• Exporting memory attributes to the system.

The MPU is useful for applications where a critical code has to be protected against the misbehavior of other tasks.

It can be used to define access rules, enforce privilege rules and separate processes.

2.1.5. Nested Vectored Interrupt Controller (NVIC)

The NVIC supports up to 32 maskable interrupts and 16 interrupt lines of Cortex-M4 with 32 priority levels. The

NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient

processing of late arriving interrupts. The NVIC maintains knowledge of the stacked or nested interrupts to enable

tail-chaining of interrupts. The processor supports both level and pulse interrupts with programmable active-high

or low control.

2.1.6. External Interrupt Controller

The external interrupt controller consists of up to 32 edge detectors for generating event/interrupt requests. Each

input line can be independently configured to select the type (interrupt or event) and the corresponding trigger

event (rising edge or falling edge or both or level). Each line can also be masked independently. A pending register

maintains the status line of the interrupt requests. Up to 21 GPIOs can be connected to 21 external interrupt lines.

2.1.7. Bus architecture

To better support various IoT applications, MT7686 adopts 32-bit multi-AHB matrix to provide low-power, fast and

flexible data operation. Table 2.1-1 shows the interconnections between bus masters and slaves.

• The bus masters include Cortex-M4, SPM, SPI master, SPI slave, SDIO master, SDIO slave, Crypto engine,

Wi-Fi connectivity system and DMA.

• The bus slaves include the Always On (AO) domain APB peripherals, Power Down (PD) domain APB

peripherals, TCM, SFC, EMI, SYSRAM, RTC SRAM and Wi-Fi connectivity system.

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