nRF9160：ARM Cortex-M33微控制器与LTE Cat-M1/Cat-NB1模组详述

nRF9160_PS_v1.0.

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nRF9160是一款由 Nordic Semiconductor 公司推出的高性能微控制器产品，其规格说明书（PS）版本为 v1.0，发行日期为2019年5月29日。这款设备基于 ARM Cortex-M33 内核，具备强大的处理能力，能够在Flash内存中运行，支持 ARM Trustzone 和 ARM Cryptocell 310，确保了安全性和加密功能。该芯片的主要特性包括： 1. **微控制器核心**: nRF9160采用了ARM Cortex-M33内核，具有高性能和低功耗的特点，支持ARM的嵌入式调试功能，如Data Watchpoint and Trace (DWT)，Embedded Trace Macrocell (ETM)，以及Instrumentation Trace Macrocell (ITM)，便于开发人员进行系统级调试。 2. **调试接口**: 提供Serial Wire Debug (SWD) 接口，方便通过外部调试工具进行编程和诊断。 3. **存储器配置**: 配备1MB Flash存储器和256kBytes的低功耗漏电流RAM，满足不同应用对存储容量的需求。 4. **安全特性**: 支持ARM Trustzone，提供硬件级别的分区，保障数据的安全性。 5. **加密支持**: 包含 ARM Cryptocell 310，为敏感数据提供了高级加密功能。 6. **外设接口**: 有多达4个SPI主/从接口，支持EasyDMA；4个I2C兼容的两线接口，同样支持EasyDMA；4个UART接口带有CTS/RTS，以及I2S和数字麦克风接口（PDM）也配备EasyDMA支持。 7. **模拟信号处理**: 提供4个脉宽调制（PWM）单元和一个12位、200ksps的ADC，具有可编程增益的8个配置通道，用于精确的模拟信号采集和控制。 8. **定时和计时功能**: 包含3个32位定时器，用于周期性任务和精确时间测量；还有2个实时时钟（RTC），用于系统时钟备份和定时。 9. **外围接口灵活性**: 包含可编程的周边接口（PPI），以适应各种定制化的系统设计需求。 10. **I/O接口**: 32个通用输入/输出引脚，为外部连接提供丰富的扩展选项。 11. **电源电压范围**: nRF9160工作在单电源3.0V至5.5V之间，适用于宽电压应用环境。 12. **集成时钟源**: 所有必要的时钟源内置，简化了系统设计。 13. **物理封装**: 采用10×16×1.04mm LGA封装，占用空间小，适合紧凑型设计。 14. **无线通信模块**: 高性能LTEmodem支持3GPP LTE Release 13的Cat-M1和Cat-NB1标准，确保在全球范围内提供可靠的蜂窝网络连接，特别适合物联网(IoT)应用，如远程监控和M2M通信。 nRF9160 PS v1.0是一份详尽的文档，概述了nRF9160作为一款多功能、高安全性的微控制器，适用于对性能、安全性和无线通信有较高要求的应用，如智能穿戴、工业自动化和物联网等领域。

Product overview

• Switching from one peripheral to another must follow a specific pattern (disable the first, then enable

the second peripheral).

3.3.2 Peripherals with shared ID

In general (with the exception of ID 0), peripherals sharing an ID and base address may not be used

simultaneously. The user can only enable one peripheral at the time on this specific ID.

When switching between two peripherals sharing an ID, the user should do the following to prevent

unwanted behavior:

• Disable the previously used peripheral.

• Disable any publish/subscribe connection to the DPPI system for the peripheral that is being disabled.

• Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF.

• Explicitly configure the peripheral that you are about to enable, and do not rely on configuration values

that may be inherited from the peripheral that was disabled.

• Enable the now configured peripheral.

See which peripherals are sharing ID in Instantiation on page 23.

3.3.3 Peripheral registers

Most peripherals feature an ENABLE register. Unless otherwise is specified in the chapter, the peripheral

registers must be configured before enabling the peripheral.

PSEL registers need to be set before a peripheral is enabled or started. Updating PSEL registers while the

peripheral is running has no effect. In order to connect a peripheral to a different GPIO, the peripheral

must be disabled, the PSEL register updated and the peripheral re-enabled. It takes four CPU cycles

between the PSEL register update and the connection between a peripheral and a GPIO becoming

effective.

Note that the peripheral must be enabled before tasks and events can be used.

Most of the register values are lost during System OFF or when a reset is triggered. Some registers will

retain their values in System OFF or for some specific reset sources. These registers are marked as retained

in the register description for a given peripheral. For more info on these retained registers' behavior, see

chapter Reset on page 54.

3.3.4 Bit set and clear

Registers with multiple single-bit bit fields may implement the set-and-clear pattern. This pattern enables

firmware to set and clear individual bits in a register without having to perform a read-modify-write

operation on the main register.

This pattern is implemented using three consecutive addresses in the register map, where the main

The SET register is used to set individual bits in the main register, while the CLR register is used to clear

individual bits in the main register. Writing 1 to a bit in SET or CLR register will set or clear the same bit in

the main register respectively. Writing 0 to a bit in SET or CLR register has no effect. Reading the SET or

CLR register returns the value of the main register.

Note: The main register may not be visible and hence not directly accessible in all cases.

3.3.5 Tasks

Tasks are used to trigger actions in a peripheral, for example to start a particular behavior. A peripheral can

implement multiple tasks with each task having a separate register in that peripheral's task register group.

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Product overview

A task is triggered when firmware writes 1 to the task register, or when the peripheral itself or another

peripheral toggles the corresponding task signal. See the figure Tasks, events, shortcuts, publish, subscribe

and interrupts on page 15.

3.3.6 Events

Events are used to notify peripherals and the CPU about events that have happened, for example a state

change in a peripheral. A peripheral may generate multiple events, where each event has a separate

An event is generated when the peripheral itself toggles the corresponding event signal, and the event

publish, subscribe and interrupts on page 15). An event register is only cleared when firmware writes 0

to it. Events can be generated by the peripheral even when the event register is set to 1.

3.3.7 Publish / Subscribe

Events and tasks from different peripherals can be connected together through the DPPI. See Tasks,

events, shortcuts, publish, subscribe and interrupts on page 15. This is done through publish /

subscribe registers in each peripheral. An event can be published onto a DPPI channel by configuring

the event's PUBLISH register. Similarly a task can subscribe to a DPPI channel by configuring the task's

SUBSCRIBE register.

See DPPI - Distributed programmable peripheral interconnect on page 82 for details.

3.3.8 Shortcuts

A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is

enabled, the associated task is automatically triggered when its associated event is generated.

Using shortcuts is equivalent to making the connection outside the peripheral and through the DPPI.

However, the propagation delay when using shortcuts is usually shorter than the propagation delay

through the DPPI.

Shortcuts are predefined, which means that their connections cannot be configured by firmware. Each

shortcut can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving

a maximum of 32 shortcuts for each peripheral.

3.3.9 Interrupts

All peripherals support interrupts. Interrupts are generated by events.

A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example,

the peripheral with ID=4 is connected to interrupt number 4 in the nested vectored interrupt controller

(NVIC).

Using registers INTEN, INTENSET, and INTENCLR, every event generated by a peripheral can be

configured to generate that peripheral's interrupt. Multiple events can be enabled to generate interrupts

simultaneously. To resolve the correct interrupt source, the event registers in the event group of

peripheral registers will indicate the source.

Some peripherals implement only INTENSET and INTENCLR registers, and the INTEN register is not

available on those peripherals. See the individual peripheral chapters for details. In all cases, reading back

the INTENSET or INTENCLR register returns the same information as in INTEN.

Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET

and INTENCLR registers.

The relationship between tasks, events, shortcuts, and interrupts is illustrated in figure Tasks, events,

shortcuts, publish, subscribe and interrupts on page 15.

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Application core

Option / Module Description Implemented

Core options

NVIC Nested vectored interrupt controller

PRIORITIES Priority bits 3

WIC Wake-up interrupt controller NO

Endianness Memory system endianness Little endian

DWT Data watchpoint and trace YES

Modules

MPU_NS Number of non-secure memory protection unit (MPU) regions 16

MPU_S Number of secure MPU regions 16

SAU Number of security attribution unit (SAU) regions 0, see SPU for more information about

secure regions.

FPU Floating-point unit YES

DSP Digital signal processing extension YES

ARMv8-M TrustZone

ARMv8-M security extensions YES

CPIF Co-processor interface NO

ETM Embedded trace macrocell YES

ITM Instrumentation trace macrocell YES

MTB Micro trace buffer NO

CTI Cross trigger interface YES

BPU Breakpoint unit YES

HTM AMBA

™

AHB trace macrocell NO

4.1.2 Electrical specification

4.1.2.1 CPU performance

The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is

executing the CoreMark

™

benchmark. It includes power regulator and clock base currents. All other blocks

are IDLE.

Symbol Description Min. Typ. Max. Units

FLASH

CPU wait states, running from flash, cache disabled 0 4

FLASHCACHE

CPU wait states, running from flash, cache enabled 0 2

RAM

CPU wait states, running from RAM 0

FLASH

CoreMark

, running from flash, cache enabled

243 CoreMark

FLASH/MHz

CoreMark per MHz, running from flash, cache enabled 3.79 CoreMark/

MHz

FLASH/mA

CoreMark per mA, running from flash, cache enabled, DC/

84 CoreMark/

4.2 Memory

The application microcontroller has embedded 1024 kB flash and 256 kB RAM for application code and

data storage.

As illustrated in Memory layout on page 21, both CPU and EasyDMA are able to access RAM via the

AHB multilayer interconnect. See AHB multilayer interconnect on page 47 and EasyDMA on page

44 for more information about AHB multilayer interconnect and EasyDMA respectively. The LTE

modem can access all application MCU memory, but typically a small portion of RAM is dedicated to data

exchange between application MCU and the modem baseband controller.

Using IAR compiler

4418_1315 v1.0

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