DDR4内存子系统硬件与布局设计要点

版权申诉

170 浏览量更新于2024-06-27 收藏 2.72MB PDF 举报

身份认证购VIP最低享 7 折!

30元优惠券

"Hardware and Layout Design Considerations for DDR4 SDRAM.pdf" 本文档主要讨论了DDR4 SDRAM在硬件设计和布局方面需要考虑的关键点和指南，适用于实施DDR4内存子系统的硬件工程师。文档中的规则和建议是板级设计师开始具体实施（如fly-by内存拓扑）的基础。特别提醒，设计者在制造电路板之前应使用仿真模型验证信号完整性、电气定时等所有方面。推荐的资源包括： 1. 应用设备参考手册中的DDR章节 2. Micron公司的网站（http://www.micron.com） 3. JEDEC的网站（http://www.jedec.com，例如DDR4 SDRAM规范）以下是文档的主要内容： 1. 文档简介：介绍了该文档的目的和适用范围，强调了在实际设计前进行仿真验证的重要性。 2. 推荐资源：列出了一些额外的、重要的参考资料来源，帮助设计师获取更多详细信息。 3. DDR4设计检查清单：可能包含了一系列设计DDR4内存系统时应考虑的关键点，例如时钟同步、数据路径设计、电源管理等。 4. 选择终端电阻：在DDR4系统中，正确选择和配置终端电阻对于信号完整性至关重要，这涉及到差分信号的匹配、反射控制以及阻抗匹配。 5. 避免VREF噪声：VREF是DDR4内存中的关键电压参考，其稳定性对数据读写精度有直接影响。设计时必须避免VREF噪声，确保信号质量。 6. 布局策略：良好的布局可以减少信号间的串扰，提高系统性能。可能包括电源和地平面的分割、信号线的布设、关键组件的位置等。 7. 时序和同步：DDR4的时序要求比DDR3更严格，设计师需要理解时钟延迟、数据有效窗口、预充电周期等概念，以确保正确操作。 8. 电源管理：DDR4引入了新的电源管理功能，如低电压工作和动态电压与频率调整，需要在硬件设计中充分考虑。 9. EMI/EMC控制：为了满足电磁兼容性标准，设计中应考虑屏蔽、滤波和接地策略。 10. 测试和调试：提供了测试接口和调试方法的建议，以便在设计完成后验证系统功能和性能。这份文档为DDR4 SDRAM的硬件设计和布局提供了一套全面的指导原则，旨在帮助工程师们避免常见问题，实现高效、可靠的内存系统设计。

资源详情

资源推荐

Table 1. DDR4 design checklist (continued)

No. Task Completed

• Bit-swap is only allowed within a nibble.

• Bit-swap across two nibbles is not allowed.

• Bit-swap across byte lanes is not allowed.

• For 32-bit or 16-bit DDR4 data bus, in the ECC byte lane only, the DQ[0], and

DQ[1] bit-swap is not allowed.

28 Ensure that each data lane properly is trace-matched to within 20 mils of its respective

differential data strobe.

• Ensure the trace matching for parts with operational data rates of higher than

1600 MT/s is within +/-5 mils.

29 When adding trace lengths to any of the DDR4 signal groups, ensure that there is at

least 25 mils between serpentine loops that are in parallel.

30 MDQS/MDQS considerations:

• Match all segment lengths between differential pairs along the entire length of the

pair. Trace match the MDQS/MDQS pair to be within +/-5 mils.

• Maintain constant line impedance along the routing path by maintaining the

required line width and trace separation for the given stackup.

• Avoid routing differential pairs adjacent to noisy signal lines or high-speed

switching devices such as clock chips.

• Differential impedance 75–95 Ω

• Differential impedance 90-95 Ω for parts with operational speeds of higher than

1600 MT/s

• Diff Gap = 4–5 mils (as DQS signals are not true differential, also known as

“pseudo differential”)

• Diff Gap = 5–8 mils, for parts with operational speeds of higher than 1600 MT/s.

Choose one of the following options to select the impedances and spacings for MDQS/

MDQS differential strobes.

Option #1 (wider traces—lower trace impedance):

• Single-ended impedance 40 Ω. The lower impedance allows traces to be slightly

closer with less cross-talk.

• Utilize wider traces if stackup allows (7–8 mils).

• Spacing to other data signals = 2x

• If not routed on the same layer as its associated data, then 4x spacing.

Option #2 (smaller traces—higher trace impedance):

• Single-ended impedance = 50 Ω

• Smaller trace widths (5–6 mils) can be used.

• Spacing between like signals (other data) should increase to 3x (for 5 mils) or

2.5x (for 6 mils), respectively.

• Do not divide the two halves of the diff pair between layers. Route the MDQS/

MDQS pair on the same critical layer as its associated data lane.

Routing address/command/control/clock bus

31 Ensure fly-by topology is used for address/command/control and clock groups. The

routing in fly-by topology should go from chip 0 to chip n and can be in the order that is

most convenient for the board design. The fly-by topology routing of address/command/

control and clock groups must end at the termination resistors that are after chip n.

Choose one of the following options to select the impedances and spacings for the

DDR4 address/command/control group.

Option #1 (wider traces—lower trace impedance):

• Single-ended impedance = 40 Ω. The lower impedance allows traces to be

slightly closer with less cross-talk.

• Utilize wider traces if stackup allows (7–8 mils).

Table continues on the next page...

DDR4 design checklist

Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces, Rev. 1, 07/2016

NXP Semiconductors 5

Table 1. DDR4 design checklist (continued)

No. Task Completed

• Spacing to other like signals = 1.5x to 2.0x

• Spacing to all other non-DDR signals = 3–4x

Option #2 (smaller traces—higher trace impedance):

• Single-ended impedance = 50 Ω

• Smaller trace widths (5–6 mils) can be used.

• Spacing between like signals should increase to 3x (for 5 mils) or 2.5x (for 6

mils), respectively

• Spacing to all other non-DDR signals = 3–4x with regards to tuning.

• Tune signals to +/-10 mils of the clock at each device.

32 Ensure clocks are routed as a differential pair, with the following recommendations:

• P-to-N tuning = +/-5 mils

• Target single-ended impedance 40–50 Ω. The lower impedance reduces cross-

talk.

• Differential impedance 75–95 Ω

• Differential impedance 90–95 Ω for parts with operational speeds of higher than

1600MT/s

• Diff Gap = set per stackup

Choose one of the following options for the DDR4 differential clocks.

Option #1 (wider traces—lower trace impedance):

• Attempt to utilize wider traces if stackup allows (7–8 mils).

• Spacing to other signals = 4x

Option #2 (smaller traces—higher trace impedance):

• Single-ended impedance = 50 Ω

• Smaller trace widths (5–6 mils) can be used.

• Spacing to other signals = 4x

NOTE:

The clock signal trace length from the memory controller to any given DDR4

chip should be longer than its corresponding strobe trace length.

33 Ensure one clock pair is used for each rank of memory in fly-by topology following the

address/command bus routing.

34 Ensure that all clock pairs are routed on the same critical layer (one referenced to a

solid ground plane).

35 Ensure the clock pair assignments are optimized to allow break-out of all pairs on a

single critical layer.

36 Ensure all clock pairs are properly trace matched to address/command/control signals

within 25 mils.

37 Ensure space from one differential pair to any other trace (this includes other

differential pairs) should be at least 25 mils.

38 If unbuffered DIMM modules are used, are all required clock pairs per DIMM slot

connected?

NOTE:

Single ranked DIMM requires one clock pair; dual ranked DIMM requires two

clock pairs.

39 Check the skew between the clock and corresponding strobe for each byte lane. The

clock and strobe trace lengths should be measured from the memory controller pin to

the DDR4 DRAM chip pin. After obtaining the MCK to DQS skew for each byte lane,

ensure max skew is less than 10 inches.

40 Ensure the MAPAR_OUT and MAPAR_ERR signals are properly connected:

Table continues on the next page...

DDR4 design checklist

Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces, Rev. 1, 07/2016

6 NXP Semiconductors

剩余25页未读，继续阅读

GJZGRB

粉丝: 2923
资源: 7737

DDR4内存子系统硬件与布局设计要点

DDR4 SDRAM存储器接口的硬件和布局设计.pdf

Hardware and Layout Design Considerations for DDR Memory Interfaces

DDR Board Design and Layout Guidelines.pdf

Requirements, and Design Considerations for 5G V2X.pdf

Use Cases Requirements and Design Considerations for 5G V2X.pdf

Hardware and Layout Design for DDR3 SDRAM

Use Cases, Requirements, and Design Considerations for 5G V2X.zi

Design considerations for hybrid applications.pdf

ISSI DDR2 SDRAM Design Considerations Guide.pdf

PCB Layout Considerations for SwitchersV2.pdf

华为Use Cases and Design+Considerations for 5GV2X+.pdf

Signal Integrity and PCB layout considerations for DDR2-800 Mb/s and DDR3 Memori

Radio Design Considerations for EDGE Handsets.

Transformer design and application considerations for nonsinusoidal load currents-00514242.pdf

Transformer design and application considerations for nonsinusoidal load currents-00502176.pdf

top-10-considerations-ecommerce-333324.pdf

rfc3347-iscsi-2002-Requirements and Design Considerations.pdf

Hardware Design Considerations for PCI Express®andSGMII

DDR3-硬件设计和-Layout-设计官方设计参考资料.pdf

最新资源