850 Chapter 10 Memory, CPLDs, and FPGAs
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Copyright © 1999 by John F. Wakerly Copying Prohibited
*10.3.5 Synchronous SRAM
A new variety of SRAM, called a synchronous SRAM (SSRAM) (“S-S-ram”),
still uses latches internally but has a clocked interface for control, address, and
data. As shown in Figure 10-26, internal edge-triggered registers
AREG
and
CREG
are placed on the signal paths for address and control. As a result, an
operation that is set up before the rising edge of the clock is performed internally
during a subsequent clock period. Register
INREG
captures the input data for
write operations, and depending on whether the device has “pipelined” or “flow-
through” outputs, register
OUTREG
is or is not provided to hold the output data
from a read operation.
The first variety of SSRAM to be introduced was the late-write SSRAM
with flow-through outputs. For a read operation, shown in Figure 10-27(a), the
control and address inputs are sampled at the rising edge of the clock, and the
synchronous SRAM
(SSRAM)
SRAM array
ADDRESS
DIN DOUT
CS
WE
AREG
CREG control logic
INREG
ADDR
CLK
CS
GW_L
DIO
OE
OUTREG
CEADS_L
only in devices with pipelined outputs
Figure 10-26
Internal structure of a
synchronous SRAM.
late-write SSRAM with
flow-through outputs