DP83848YB单端口10/100Mb/s以太网物理层收发器

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"DP83848YB PHYTERExtreme Temperature Single Port 10/100Mb/s Ethernet Physical Layer Transceiver" DP83848YB是国家半导体公司（National Semiconductor Corporation）推出的高速以太网物理层收发器，支持10/100Mb/s的以太网连接速度。该设备符合IEEE 802.3u标准，能够在极端温度范围（-40°C to 125°C）下稳定工作，非常适合恶劣环境中的应用，例如无线远程基站、汽车/交通和工业控制应用。 DP83848YB设备具有高度的可靠性和丰富的功能特性，包括增强的ESD保护、MII和RMII接口以提供最大灵活性的MPU选择，所有这些功能都封装在一个48针LQFP封装中。该设备的设计目标是为了满足恶劣环境中的应用需求，同时也满足了用户对ease of implementation的需求。 DP83848YB的主要特性包括： * 支持10/100Mb/s的以太网连接速度 * 符合IEEE 802.3u标准 * 极端温度范围（-40°C to 125°C）下稳定工作 * 高度可靠性和丰富的功能特性 * 增强的ESD保护 * MII和RMII接口以提供最大灵活性的MPU选择 * 48针LQFP封装 DP83848YB的应用场景包括： * 无线远程基站 * 汽车/交通 * 工业控制 * 恶劣环境中的其他应用在实际应用中，DP83848YB可以帮助用户快速实现以太网连接，满足恶劣环境中的应用需求，同时也提供了高度的可靠性和灵活性。此外，DP83848YB还可以应用于其他领域，例如： * 工业自动化 * 医疗设备 * 安全监控 * 智能家居 DP83848YB是一个功能强大、可靠性高、灵活性强的高速以太网物理层收发器，能够满足恶劣环境中的应用需求，广泛应用于各种领域。

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DP83848YB

1.8 10 Mb/s and 100 Mb/s PMD Interface

1.9 Special Connections

1.10 Power Supply Pins

Signal Name Type Pin # Description

TD-, TD+ I/O 16, 17 Differential common driver transmit output (PMD Output Pair).

These differential outputs are automatically configured to either

10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operation, this pair can be used as the Re-

ceive Input pair.

These pins require 3.3V bias for operation.

RD-, RD+ I/O 13, 14 Differential receive input (PMD Input Pair). These differential in-

puts are automatically configured to accept either 100BASE-TX

or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the

Transmit Output pair.

These pins require 3.3V bias for operation.

Signal Name Type Pin # Description

RBIAS I 24 Bias Resistor Connection. A 4.87 k ? 1% resistor should be con-

nected from RBIAS to GND.

PFBOUT O 23 Power Feedback Output. Parallel caps, 10 μ　F (Tantalum pre-

ferred) and 0.1 μF, should be placed close to the PFBOUT. Con-

nect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See

Section 5.4 for proper placement pin.

PFBIN1

PFBIN2

I 18

Power Feedback Input. These pins are fed with power from

PFBOUT pin. A small capacitor of 0.1 μF should be connected

close to each pin.

Note: Do not supply power to these pins other than from

PFBOUT.

RESERVED I/O 20, 21 RESERVED: These pins must be pulled-up through 2.2 k ? resis-

tors to AVDD33 supply.

Signal Name Pin # Description

IOVDD33 32, 48 I/O 3.3V Supply

IOGND 35, 47 I/O Ground

DGND 36 Digital Ground

AVDD33 22 Analog 3.3V Supply

AGND 15, 19 Analog Ground

GNDPAD 49 Ground PAD

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DP83848YB

2.0 Configuration

This section includes information on the various configura-

tion options available with the DP83848YB. The configura-

tion options described below include:

— Auto-Negotiation

— PHY Address and LEDs

— Half Duplex vs. Full Duplex

— Isolate mode

— Loopback mode

— BIST

2.1 Auto-Negotiation

The Auto-Negotiation function provides a mechanism for

exchanging configuration information between two ends of

a link segment and automatically selecting the highest per-

formance mode of operation supported by both devices.

Fast Link Pulse (FLP) Bursts provide the signalling used to

communicate Auto-Negotiation abilities between two

devices at each end of a link segment. For further detail

regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83848YB supports four differ-

ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full

Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),

so the inclusion of Auto-Negotiation ensures that the high-

est performance protocol will be selected based on the

advertised ability of the Link Partner. The Auto-Negotiation

function within the DP83848YB can be controlled either by

internal register access or by the use of the AN_EN, AN1

and AN0 pins.

2.1.1 Auto-Negotiation Pin Control

The state of AN_EN, AN0 and AN1 determines whether

the DP83848YB is forced into a specific mode or Auto-

Negotiation will advertise a specific ability (or set of abili-

ties) as given in Table 1. These pins allow configuration

options to be selected without requiring internal register

access.

The state of AN_EN, AN0 and AN1, upon power-up/reset,

determines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or

reset can be changed at any time by writing to the Basic

Mode Control Register (BMCR) at address 0x00h.

2.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83848YB trans-

mits the abilities programmed into the Auto-Negotiation

Advertisement register (ANAR) at address 04h via FLP

Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-

Duplex, and Full Duplex modes may be selected.

Auto-Negotiation Priority Resolution:

— (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex

— (3) 10BASE-T Full Duplex

— (4) 10BASE-T Half Duplex (Lowest Priority)

The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the

Auto-Negotiation process. When Auto-Negotiation is dis-

abled, the Speed Selection bit in the BMCR controls

switching between 10 Mb/s or 100 Mb/s operation, and the

Duplex Mode bit controls switching between full duplex

operation and half duplex operation. The Speed Selection

and Duplex Mode bits have no effect on the mode of oper-

ation when the Auto-Negotiation Enable bit is set.

The Link Speed can be examined through the PHY Status

achieved.

The Basic Mode Status Register (BMSR) indicates the set

of available abilities for technology types, Auto-Negotiation

ability, and Extended Register Capability. These bits are

permanently set to indicate the full functionality of the

DP83848YB (only the 100BASE-T4 bit is not set since the

DP83848YB does not support that function).

The BMSR also provides status on:

— Whether or not Auto-Negotiation is complete

— Whether or not the Link Partner is advertising that a re-

mote fault has occurred

— Whether or not valid link has been established

— Support for Management Frame Preamble suppression

The Auto-Negotiation Advertisement Register (ANAR)

indicates the Auto-Negotiation abilities to be advertised by

the DP83848YB. All available abilities are transmitted by

default, but any ability can be suppressed by writing to the

Table 1. Auto-Negotiation Modes

AN_EN AN1 AN0 Forced Mode

0 0 0 10BASE-T, Half-Duplex

0 0 1 10BASE-T, Full-Duplex

0 1 0 100BASE-TX, Half-Duplex

0 1 1 100BASE-TX, Full-Duplex

AN_EN AN1 AN0 Advertised Mode

1 0 0 10BASE-T, Half/Full-Duplex

1 0 1 100BASE-TX, Half/Full-Duplex

1 1 0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

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DP83848YB

ANAR. Updating the ANAR to suppress an ability is one

way for a management agent to change (restrict) the tech-

nology that is used.

The Auto-Negotiation Link Partner Ability Register

(ANLPAR) at address 05h is used to receive the base link

code word as well as all next page code words during the

negotiation. Furthermore, the ANLPAR will be updated to

either 0081h or 0021h for parallel detection to either 100

Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indi-

cates additional Auto-Negotiation status. The ANER pro-

vides status on:

— Whether or not a Parallel Detect Fault has occurred

— Whether or not the Link Partner supports the Next Page

function

— Whether or not the DP83848YB supports the Next Page

function

— Whether or not the current page being exchanged by

Auto-Negotiation has been received

— Whether or not the Link Partner supports Auto-Negotia-

tion

2.1.3 Auto-Negotiation Parallel Detection

The DP83848YB supports the Parallel Detection function

as defined in the IEEE 802.3u specification. Parallel Detec-

tion requires both the 10 Mb/s and 100 Mb/s receivers to

monitor the receive signal and report link status to the

Auto-Negotiation function. Auto-Negotiation uses this infor-

mation to configure the correct technology in the event that

the Link Partner does not support Auto-Negotiation but is

transmitting link signals that the 100BASE-TX or 10BASE-

T PMAs recognize as valid link signals.

If the DP83848YB completes Auto-Negotiation as a result

of Parallel Detection, bits 5 and 7 within the ANLPAR regis-

ter will be set to reflect the mode of operation present in the

Link Partner. Note that bits 4:0 of the ANLPAR will also be

set to 00001 based on a successful parallel detection to

indicate a valid 802.3 selector field. Software may deter-

mine that negotiation completed via Parallel Detection by

reading a zero in the Link Partner Auto-Negotiation Able bit

once the Auto-Negotiation Complete bit is set. If configured

for parallel detect mode and any condition other than a sin-

gle good link occurs then the parallel detect fault bit will be

set.

2.1.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted

at any time by setting bit 9 (Restart Auto-Negotiation) of the

BMCR to one. If the mode configured by a successful Auto-

Negotiation loses a valid link, then the Auto-Negotiation

process will resume and attempt to determine the configu-

ration for the link. This function ensures that a valid config-

uration is maintained if the cable becomes disconnected.

A renegotiation request from any entity, such as a manage-

ment agent, will cause the DP83848YB to halt any transmit

data and link pulse activity until the break_link_timer

expires (~1500 ms). Consequently, the Link Partner will go

into link fail and normal Auto-Negotiation resumes. The

DP83848YB will resume Auto-Negotiation after the

break_link_timer has expired by issuing FLP (Fast Link

Pulse) bursts.

2.1.5 Enabling Auto-Negotiation via Software

It is important to note that if the DP83848YB has been ini-

tialized upon power-up as a non-auto-negotiating device

(forced technology), and it is then required that Auto-Nego-

tiation or re-Auto-Negotiation be initiated via software,

bit 12 (Auto-Negotiation Enable) of the Basic Mode Control

Auto-Negotiation function to take effect.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately

2-3 seconds to complete. In addition, Auto-Negotiation with

next page should take approximately 2-3 seconds to com-

plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full

description of the individual timers related to Auto-Negotia-

tion.

2.2 Auto-MDIX

When enabled, this function utilizes Auto-Negotiation to

determine the proper configuration for transmission and

reception of data and subsequently selects the appropriate

MDI pair for MDI/MDIX operation. The function uses a ran-

dom seed to control switching of the crossover circuitry.

This implementation complies with the corresponding IEEE

802.3 Auto-Negotiation and Crossover Specifications.

Auto-MDIX is enabled by default and can be configured via

strap or via PHYCR (0x19h) register, bits [15:14].

Neither Auto-Negotiation nor Auto-MDIX is required to be

enabled in forcing crossover of the MDI pairs. Forced

crossover can be achieved through the FORCE_MDIX bit,

bit 14 of PHYCR (0x19h) register.

Note: Auto-MDIX will not work in a forced mode of opera-

tion.

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