"TI-DS99R104.pdf: FPD-Link解串器及其特性"
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The DS99R103/DS99R104 chipset, as described in the TI-DS99R104.pdf document, is a high-speed, DC-balanced 24-bit LVDS (Low-Voltage Differential Signaling) serializer and deserializer designed for data transmission over long distances. This chipset is capable of translating a 24-bit parallel bus into a fully transparent LVDS serial stream with embedded clock information, operating within a frequency range of 3-40MHz. The chipset features a 24:1 and 1:24 data transmission ratio, allowing for efficient data/control transmission with minimal signal degradation.
One of the key features of the DS99R103/DS99R104 chipset is its ability to drive shielded twisted-pair cables, making it suitable for use in a variety of high-speed data transmission applications. This capability enables the chipset to maintain signal integrity and reduce electromagnetic interference, ensuring reliable data transmission in challenging environments.
The DS99R103/DS99R104 chipset is designed to meet the demands of high-speed data transmission applications, offering a reliable and efficient solution for translating parallel bus interfaces into LVDS serial streams. Whether used in industrial automation, digital signage, or other applications requiring high-speed data transmission, the DS99R103/DS99R104 chipset provides a robust and versatile solution for interfacing with LVDS serial streams.
In conclusion, the DS99R103/DS99R104 chipset is a versatile and high-performance solution for translating parallel bus interfaces into LVDS serial streams. With its ability to operate within a wide frequency range, drive shielded twisted-pair cables, and maintain signal integrity, this chipset offers a reliable and efficient solution for high-speed data transmission applications. Its transparent data/control transmission and DC-balanced LVDS serial stream make it an ideal choice for a wide range of applications requiring robust and high-speed data transmission capabilities.
DS99R103, DS99R104
SNLS241D –MARCH 2007–REVISED APRIL 2013
www.ti.com
Serializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter Test Conditions Min Typ Max Units
t
HZD
DOUT ± HIGH to TRI-STATE Delay R
L
= 100Ω, 15 ns
C
L
= 10 pF to GND
t
LZD
DOUT ± LOW to TRI-STATE Delay 15 ns
(Figure 6)
(2)
t
ZHD
DOUT ± TRI-STATE to HIGH Delay 200 ns
t
ZLD
DOUT ± TRI-STATE to LOW Delay 200 ns
t
PLD
Serializer PLL Lock Time R
L
= 100Ω, (Figure 7) 10 ms
t
SD
Serializer Delay R
L
= 100Ω, (Figure 8) 3.5T + 3.5T +
ns
VODSEL = L, TRFB = H 2.85 10
R
L
= 100Ω, (Figure 8) 3.5T + 3.5T +
ns
VODSEL = L, TRFB = L 2.85 10
TxOUT_E_O TxOUT_Eye_Opening (respect to 3–40 MHz UI
0.68
ideal) (Figure 9)
(3)(4) (5)
(2) When the Serializer output is at TRI-STATE, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(3) t
JIT
(@BER of 10e-9) specifies the allowable jitter on TCLK. t
JIT
not included in TxOUT_E_O parameter.
(4) TxOUT_E_O is affected by pre-emphasis value.
(5) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter Test Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver out Clock Period t
RCP
= t
TCP
(1)
RCLK 25 T 333 ns
t
RDC
RCLK Duty Cycle RCLK 45 50 55 %
t
CLH
LVCMOS Low-to-High Transition Time C
L
= 8 pF ROUT [23:0], 2.5 3.5 ns
(lumped load) LOCK, RCLK
t
CHL
LVCMOS High-to-Low Transition Time
2.5 3.5 ns
(Figure 11)
t
ROS
ROUT (7:0) Setup Data to RCLK (Figure 15) ROUT [7:0] (0.40)*
(29/56)*t
RCP
ns
(Group 1) t
RCP
t
ROH
ROUT (7:0) Hold Data to RCLK (0.40)*
(27/56)*t
RCP
ns
(Group 1) t
RCP
t
ROS
ROUT (15:8) Setup Data to RCLK (Figure 15) ROUT [15:8], (0.40)*
0.5*t
RCP
ns
(Group 2) LOCK t
RCP
t
ROH
ROUT (15:8) Hold Data to RCLK (0.40)*
0.5*t
RCP
ns
(Group 2) t
RCP
t
ROS
ROUT (23:16) Setup Data to RCLK (Figure 15) ROUT (0.40)*
(27/56)*t
RCP
ns
(Group 3) [23:16] t
RCP
t
ROH
ROUT (23:16) Hold Data to RCLK (0.40)*
(29/56)*t
RCP
ns
(Group 3) t
RCP
t
HZR
HIGH to TRI-STATE Delay (Figure 13) ROUT [23:0], 3 10 ns
RCLK, LOCK
t
LZR
LOW to TRI-STATE Delay 3 10 ns
t
ZHR
TRI-STATE to HIGH Delay 3 10 ns
t
ZLR
TRI-STATE to LOW Delay 3 10 ns
t
DD
Deserializer Delay (Figure 12) RCLK [4+(3/56)]T [4+(3/56)]T ns
+5.9 +18.5
t
DRDL
Deserializer PLL Lock Time from (Figure 14)
(2)(1)
3 MHz 5 50 ms
Powerdown
40 MHz 5 50 ms
RxIN_TOL_L Receiver INput TOLerance Left (Figure 16)
(3)(1)(4)
3 MHz–40
0.25 UI
MHz
RxIN_TOL_R Receiver INput TOLerance Right (Figure 16)
(3)(1)(4)
3 MHz–40
0.25 UI
MHz
(1) Specification is ensured by characterization and is not tested in production.
(2) The Deserializer PLL lock time (t
DRDL
) may vary depending on input data patterns and the number of transitions within the pattern.
(3) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see TI’s AN-1217 (Literature Number SNLA053) for detail.
(4) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
6 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R103 DS99R104
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