LatticeECP3系列数据表：集成SDI转HDMI方案与高密度逻辑设计

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本文档是Lattice Semiconductor公司关于LatticeECP3 EAFamily的数据手册，版本为DS1021 Version 02.4EA，发布日期为2013年9月。该系列FPGA（Field-Programmable Gate Array）旨在提供更高的逻辑密度，以实现系统集成的增强。主要特点包括： 1. **逻辑密度提升**：LatticeECP3集成了17K至149K个Look-Up Tables (LUTs)，以及116至586个输入/输出(I/O)端口，这使得设计者能够在单个芯片上整合更多的功能。 2. **嵌入式SerDes**：支持多种数据速率，从150Mbps到3.2Gbps，适用于通用8b/10b编码、10位和8位模式的串行收发器。此外，针对不同的协议，如PCIe、SONET/SDH、以太网（1GbE, SGMII, XAUI）、CPRI、SMPTE 3G和Serial RapidIO，可以达到高达16条通道。 3. **sysDSP™技术**：这款FPGA配备了全可级联的slice架构，包含12至160个高性能乘法和累加单元，支持54位算术逻辑单元(Alu)操作。它还具备时间分片多工MAC（Multiplication Accumulation）功能，支持半精度36x36、两个18x18或四个9x9的乘法运算，以及舍入和截断操作。 4. **应用范围广泛**：由于其灵活的性能和广泛的接口支持，LatticeECP3 EAFamily适合于各种应用领域，包括但不限于高速数据传输、通信系统、视频接口转换（如SDI转HDMI），以及需要高计算密集型任务的场景。总结来说，LatticeECP3 EAFamily DataSheet是一份详细的技术文档，提供了设计者在选择和使用这种FPGA时所需的关键规格和特性信息，对于那些寻求在有限空间内集成大量功能、高速数据处理和接口兼容性的工程师来说，它是一个宝贵的资源。通过深入理解并利用这些特性，开发人员可以构建出高效且高度集成的系统解决方案。

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Architecture

LatticeECP3 Family Data Sheet

Primary Clock Routing

The purpose of the primary clock routing is to distribute primary clock sources to the destination quadrants of the

device. A global primary clock is a primary clock that is distributed to all quadrants. The clock routing structure in

LatticeECP3 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The pri-

mary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources

are connected to these muxes. Figure 2-12 shows the clock routing for one quadrant. Each quadrant mux is identi-

cal. If desired, any clock can be routed globally.

Figure 2-12. Per Quadrant Primary Clock Selection

Dynamic Clock Control (DCC)

The DCC (Quadrant Clock Enable/Disable) feature allows internal logic control of the quadrant primary clock net-

work. When a clock network is disabled, all the logic fed by that clock does not toggle, reducing the overall power

consumption of the device.

Dynamic Clock Select (DCS)

The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent

input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog-

gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the

DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7

(see Figure 2-12).

Figure 2-13 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed

to other modes. For more information about the DCS, please see the list of technical documentation at the end of

this data sheet.

Figure 2-13. DCS Waveforms

CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7

63:1 63:1 63:1 63:1 58:1 58:1 58:1 58:163:1 63:1

DCC DCC DCC DCC DCS DCSDCC DCC

8 Primary Clocks (CLK0 to CLK7) per Quadrant

PLLs + DLLs + CLKDIVs + PCLK PIOs + SERDES Quads

CLK0

SEL

DCSOUT

CLK1

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LatticeECP3系列数据表：集成SDI转HDMI方案与高密度逻辑设计

lattice hispi

LatticeECP3 Family Data Sheet

LATTICE-ECP3-datasheet

LatticeECP3MemoryUsageGuide

LatticeECP3-35EAPinout

LatticeECP3High-SpeedIOInterface

LatticeECP3设计的FPGA视频协议开发技术

LatticeECP3 sysDSP块的嵌入式信号处理功能

FPGA视频协议开发技术在LatticeECP3设计的应用

LatticeECP3系列FPGA 官方技术文档资料合集.zip

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