ModelSim SE 6.3f Reference Manual: Detailed Command Guide

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"ModelSim SE 参考手册 V6.3f (modelsim_se_ref.pdf)" ModelSim SE 是一款广泛使用的仿真器，尤其在Verilog语言的数字逻辑设计领域中非常流行。该参考手册V6.3f是针对该软件的新版本，提供了全面的命令解释和详细说明，帮助用户理解和使用ModelSim SE的功能。该手册涵盖了多个关键知识点： 1. **ModelSim基础知识**：介绍ModelSim SE的基本架构和工作流程，包括如何启动、设置工程、编译源代码以及运行仿真。 2. **Verilog支持**：ModelSim SE支持Verilog HDL（硬件描述语言），详细解释了如何处理Verilog模块、接口、任务、函数、系统任务和属性等。 3. **命令行界面**：手册详细列出了ModelSim的命令行界面命令，如`vlib`用于创建库，`vlog`用于编译Verilog源文件，`vsim`用于启动仿真，以及`run`命令来执行仿真。 4. **图形用户界面**：介绍了ModelSim的Wave窗口，用于波形显示和调试，以及如何使用它来观察信号变化。 5. **调试工具**：包括断点设置、单步执行、变量查看、覆盖率分析等功能的使用方法。 6. **错误和警告处理**：解释了如何理解和解决在编译和仿真过程中遇到的错误和警告信息。 7. **自定义脚本**：ModelSim支持Tcl/Tk脚本，手册会指导用户如何编写和运行这些脚本来自动化常见任务。 8. **性能优化**：提供了一些策略和技巧，帮助用户提高仿真速度和降低内存占用。 9. **库管理**：详细说明了如何创建、管理库，以及导入和导出库的设置。 10. **接口与集成**：讨论了ModelSim与其他设计工具（如综合器、形式验证工具等）的接口和集成方法。请注意，尽管手册包含了详尽的信息，但Mentor Graphics保留权利随时更改产品规格和信息，因此读者应始终与官方更新保持同步。此外，手册中的任何内容都不构成产品销售或授权的条款，具体协议应以书面合同为准。阅读并理解这份ModelSim SE参考手册是充分利用这款强大仿真工具的关键，它能帮助设计者高效地测试和调试Verilog代码，确保数字电路设计的正确性。

ModelSim SE Reference Manual, v6.3e

Syntax and Conventions

File and Directory Pathnames

February 2008

File and Directory Pathnames

Several ModelSim commands have arguments that point to files or directories. For example, the

-y argument to vlog specifies the Verilog source library directory to search for undefined

modules. Spaces in file pathnames must be escaped or the entire path must be enclosed in

quotes. For example:

vlog top.v -y C:/Documents\ and\ Settings/projects/dut

vlog top.v -y "C:/Documents and Settings/projects/dut"

Design Object Names

Design objects are organized hierarchically. Each of the following objects creates a new level in

the hierarchy:

• VHDL — component instantiation statement, block statement, and package

• Verilog — module instantiation, named fork, named begin, task and function

• SystemVerilog — class, package, program, and interface

• SystemC — module instantiation

Object Name Syntax

The syntax for specifying object names in ModelSim is as follows:

[<datasetName><datasetSeparator>][<pathSeparator>][<hierarchicalPath>]

<objectName>[<elementSelection>]

where

• datasetName — is the logical name of the WLF file in which the object exists. The

currently active simulation is the “sim” dataset. Any loaded WLF file is referred to by

the logical name specified when the WLF file was loaded. Refer to the chapter

“Recording Simulation Results With Datasets” in the User’s Manual for more

information.

• datasetSeparator — is the character used to terminate the dataset name. The default is

’:’, though a different character (other than ’\’) may be specified as the dataset separator

via the DatasetSeparator variable in the modelsim.ini file. The default is ':'. This

character must be different than the pathSeparator character.

• pathSeparator — is the character used to separate hierarchical object names. Normally,

'/' is used for VHDL and '.' is used for Verilog, although other characters (except '\') may

be specified via the PathSeparator variable in the modelsim.ini file. This character must

ModelSim SE Reference Manual, v6.3e

Syntax and Conventions

File and Directory Pathnames

February 2008

A relative name does not start with a path separator and may or may not include a dataset name

or a hierarchical path (e.g., u1/data or view:clk). A relative name is relative to the current

context in the current or specified dataset.

A fully-rooted name starts with a path separator and includes a hierarchical path to an object

(e.g., /top/u1/clk).There is a special case of a fully-rooted name where the top-level design unit

name can be unspecified (e.g., /u1/clk). In this case, the first top-level instance in the design is

assumed.

An absolute name is an exactly specified hierarchical name containing a dataset name and a

fully rooted name (e.g., sim:/top/u1/clk).

The current dataset is used when accessing objects where a dataset name is not specified as part

of the name. The current dataset is determined by the dataset currently selected in the Structure

window or by the last dataset specified in an environment.

The current context in the current or specified dataset is used when accessing objects with

relative or simple names. The current context is either the current process, if any, or the current

instance if there is no current process or the current process is not in the current instance. The

situation of the current process not being in the current instance can occur, for example, by

selecting a different instance in the Structure tab or by using the environment to set the current

context to a different instance.

Table 1-2 contains examples of various ways of specifying object names.

Table 1-2. Examples of Object Names

Object Name Description

clk specifies the object clk in the current context

/top/clk specifies the object clk in the top-level design unit.

/top/block1/u2/clk specifies the object clk, two levels down from the top-level

design unit

block1/u2/clk specifies the object clk, two levels down from the current

context

array_sig[4] specifies an index of an array object

{array_sig(1 to 10)} specifies a slice of an array object in VHDL or SystemC;

see Escaping Brackets and Spaces in Array Slices for more

information

{mysignal[31:0]} specifies a slice of an array object in Verilog or SystemC;

see Escaping Brackets and Spaces in Array Slices for more

information

record_sig.field specifies a field of a record, a C++ class or structure

member, or a C++ base class

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