ARM与Thumb-2指令集快速参考

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"该资源是关于ARM和Thumb-2指令集的快速参考卡片，涵盖了这两种指令集的关键信息，包括操作数、寄存器列表、处理器状态寄存器（PSR）字段以及各种操作标志等。" ARM和Thumb-2指令集是ARM架构中的两种主要指令集，它们用于控制和执行微处理器上的操作。Thumb-2是Thumb指令集的一个扩展，旨在提供更高的代码密度，同时保持与原始Thumb指令集的向后兼容性。在ARM指令集中，指令通常以32位的形式存在，而Thumb-2指令集则包含16位和32位两种长度的指令，以适应不同的性能和空间需求。"Key to Tables"部分提到的符号如Rm{,<opsh>}表示一个可以被常量偏移的寄存器，<Operand2>则表示灵活的操作数2，可能涉及到位移和旋转操作。 "Rm{,<opsh>}"中的"Rm"是一个寄存器，可以被一个常量所移位，"opsh"代表了可以选择的移位操作，如逻辑左移、逻辑右移、算术右移或循环右移。这些移位操作在处理数据时非常有用，例如在位操作、算术运算和数据对齐中。寄存器列表（<reglist>）以花括号包围，用逗号分隔，允许一次性操作多个寄存器。如果列表中包含了PC（程序计数器），则需要特别注意，因为这通常涉及到跳转指令。在某些情况下，列表中不能包含PC（<reglist-PC>），而在其他情况下则可以（<reglist+PC>）。 PSR（Processor Status Register）是处理器状态寄存器，包含了许多标志位，如条件标志C、V等，它们反映了最近的算术操作结果。在早期的ARM架构版本中，某些标志的行为可能是不可预测的，但在v5及以后的版本中，这些标志会保持不变。 "Rs|sh"表示可以是寄存器Rs或者立即数作为移位值。表格中的"ARM architecture versions"可能列出了不同版本的ARM架构中对于各种移位类型允许的值。 "iflags"指的是中断标志，可能包括a（abort）、i（interrupt）和f（fast interrupt）。这些标志用于控制和响应处理器的中断请求。 "x,y"可能指代半寄存器，其中x代表低16位（[15:0]），y代表高16位（[31:16]），这对于处理半寄存器操作和双字操作很有帮助。 <p_mode>是指处理器模式，ARM架构提供了多种处理器模式，如用户模式、系统模式、中断模式等，这些模式在处理不同级别的权限和异常时至关重要。 "imm8m"是ARM指令集中的一种8位立即数，通过右旋一个偶数位来形成一个32位的常量，这在进行位操作或形成特定地址时非常有用。 "SP"通常代表堆栈指针，是处理器用来跟踪内存栈顶部位置的寄存器，特别是在处理函数调用和局部变量时。这个参考卡片为理解和使用ARM及Thumb-2指令集提供了快速的查阅指南，涵盖了从基本操作到高级特性的方方面面。对于开发嵌入式系统或进行ARM平台编程的工程师来说，它是一个宝贵的工具。

ARM

and Thumb

-2 Instruction Set

Quick Reference Card

Key to Tables

Rm {, <opsh>} See Table Register, optionally shifted by constant

<Operand2> See Table Flexible Operand 2. Shift and rotate are only available as part of Operand2. <reglist> A comma-separated list of registers, enclosed in braces { and }.

<fields> See Table PSR fields. <reglist-PC> As <reglist>, must not include the PC.

<PSR> Either CPSR (Current Processor Status Register) or SPSR (Saved Processor Status Register) <reglist+PC> As <reglist>, including the PC.

C*, V* Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later. +/- + or –. (+ may be omitted.)

<Rs|sh> Can be Rs or an immediate shift value. The values allowed for each shift type are the same as those § See Table ARM architecture versions.

shown in Table Register, optionally shifted by constant. <iflags> Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt).

x,y B meaning half-register [15:0], or T meaning [31:16]. <p_mode> See Table Processor Modes

<imm8m> ARM: a 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits. SPm SP for the processor mode specified by <p_mode>

Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bit <lsb> Least significant bit of bitfield.

pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00. <width> Width of bitfield. <width> + <lsb> must be <= 32.

<prefix> See Table Prefixes for Parallel instructions {X} RsX is Rs rotated 16 bits if X present. Otherwise, RsX is Rs.

{IA|IB|DA|DB} Increment After, Increment Before, Decrement After, or Decrement Before. {!} Updates base register after data transfer if ! present (pre-indexed).

IB and DA are not available in Thumb state. If omitted, defaults to IA. {S} Updates condition flags if S present.

<size> B, SB, H, or SH, meaning Byte, Signed Byte, Halfword, and Signed Halfword respectively. {T}

User mode privilege if T present.

SB and SH are not available in STR instructions. {R} Rounds result to nearest if R present, otherwise truncates result.

Operation § Assembler S updates Action Notes

Add Add ADD{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 N

with carry ADC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 + Carry N

wide T2 ADD Rd, Rn, #<imm12> Rd := Rn + imm12, imm12 range 0-4095 T, P

saturating {doubled} 5E Q{D}ADD Rd, Rm, Rn Rd := SAT(Rm + Rn) doubled: Rd := SAT(Rm + SAT(Rn * 2)) Q

Address Form PC-relative address ADR Rd, <label> Rd := <label>, for <label> range from current instruction see Note L N, L

Subtract Subtract SUB{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 N

with carry SBC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 – NOT(Carry) N

wide T2 SUB Rd, Rn, #<imm12> N Z C V Rd := Rn – imm12, imm12 range 0-4095 T, P

reverse subtract RSB{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn N

reverse subtract with carry RSC{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn – NOT(Carry) A

saturating {doubled} 5E Q{D}SUB Rd, Rm, Rn Rd := SAT(Rm – Rn) doubled: Rd := SAT(Rm – SAT(Rn * 2)) Q

Exception return without stack SUBS PC, LR, #<imm8> PC = LR – imm8, CPSR = SPSR(current mode), imm8 range 0-255. T

Parallel

arithmetic

Halfword-wise addition 6 <prefix>ADD16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[31:16], Rd[15:0] := Rn[15:0] + Rm[15:0] G

Halfword-wise subtraction 6 <prefix>SUB16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[31:16], Rd[15:0] := Rn[15:0] – Rm[15:0] G

Byte-wise addition 6 <prefix>ADD8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] + Rm[31:24], Rd[23:16] := Rn[23:16] + Rm[23:16],

Rd[15:8] := Rn[15:8] + Rm[15:8], Rd[7:0] := Rn[7:0] + Rm[7:0]

Byte-wise subtraction 6 <prefix>SUB8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] – Rm[31:24], Rd[23:16] := Rn[23:16] – Rm[23:16],

Rd[15:8] := Rn[15:8] – Rm[15:8], Rd[7:0] := Rn[7:0] – Rm[7:0]

Halfword-wise exchange, add, subtract 6 <prefix>ASX Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[15:0], Rd[15:0] := Rn[15:0] – Rm[31:16] G

Halfword-wise exchange, subtract, add 6 <prefix>SAX Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[15:0], Rd[15:0] := Rn[15:0] + Rm[31:16] G

Unsigned sum of absolute differences 6 USAD8 Rd, Rm, Rs Rd := Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])

+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])

and accumulate 6 USADA8 Rd, Rm, Rs, Rn Rd := Rn + Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])

+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])

Saturate Signed saturate word, right shift 6 SSAT Rd, #<sat>, Rm{, ASR <sh>} Rd := SignedSat((Rm ASR sh), sat). <sat> range 1-32, <sh> range 1-31. Q, R

Signed saturate word, left shift 6 SSAT Rd, #<sat>, Rm{, LSL <sh>} Rd := SignedSat((Rm LSL sh), sat). <sat> range 1-32, <sh>

range 0-31. Q

Signed saturate two halfwords 6 SSAT16 Rd, #<sat>, Rm Rd[31:16] := SignedSat(Rm[31:16], sat),

Rd[15:0] := SignedSat(Rm[15:0], sat). <sat> range 1-16.

Unsigned saturate word, right shift 6 USAT Rd, #<sat>, Rm{, ASR <sh>} Rd := UnsignedSat((Rm ASR sh), sat). <sat> range 0-31, <sh> range 1-31. Q, R

Unsigned saturate word, left shift 6 USAT Rd, #<sat>, Rm{, LSL <sh>} Rd := UnsignedSat((Rm LSL sh), sat). <sat> range 0-31, <sh> range 0-31. Q

Unsigned saturate two halfwords 6 USAT16 Rd, #<sat>, Rm Rd[31:16] := UnsignedSat(Rm[31:16], sat),

Rd[15:0] := UnsignedSat(Rm[15:0], sat). <sat> range 0-15.

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