NXP MFRC522: 13.56MHz 无接触读写器数据手册

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"NXP RC522是一款专用于IC卡读写的接触式射频识别（RFID）芯片，主要支持MIFARE系列的各种协议，包括MIFARE Mini、MIFARE 1K、MIFARE 4K、MIFARE Ultralight、MIFARE DESFire EV1和MIFARE Plus。这款芯片集成了13.56MHz的读写功能，符合ISO/IEC14443A/MIFARE模式标准。" NXP RC522是一款由NXP半导体公司生产的高性能读写器集成电路，设计用于非接触式通信。该芯片在13.56MHz频率下工作，能够支持多种MIFARE系列的RFID协议，这些协议涵盖了不同容量和安全级别的智能卡应用。MIFARE系列协议的通用名称是MIFARE，包括了小型、标准型、增强型、超轻型以及带有DESFire加密的安全产品。 MFRC522的内部发射器可以驱动一个设计用于与ISO/IEC14443A/MIFARE卡片和应答器通信的读写天线，无需额外的主动电路。接收模块则提供了对来自兼容ISO/IEC14443A/MIFARE卡片和应答器信号的高效解调和解码。数字模块负责处理完整的ISO/IEC14443A帧结构以及错误检测功能，包括奇偶校验和循环冗余校验（CRC）。在硬件特性方面，MFRC522具有以下关键功能： 1. **自动调谐**：芯片能自动调整天线的谐振频率，确保与目标卡片的最佳通信。 2. **防碰撞算法**：支持ISO/IEC14443A的防碰撞算法，允许多个卡片同时存在于读写器的射频场中而不会产生数据冲突。 3. **安全机制**：提供AES加密和解密功能，以支持MIFARE DESFire EV1和MIFARE Plus等高级安全协议。 4. **能量捕获模式**：能够从卡片获取部分能量，实现无源操作。 5. **I2C和SPI接口**：提供与微控制器连接的多种接口选项，方便系统集成。 6. **电源管理**：具有低功耗模式，适应不同应用场景。 MFRC522广泛应用在各种RFID系统中，如公交卡、门禁系统、电子支付、库存管理和物联网设备的身份验证等。其强大的功能和灵活性使其成为开发非接触式应用的理想选择。在设计使用NXP RC522的系统时，需要考虑天线设计、电源管理、数据安全以及与微控制器的接口设计等多个方面，以确保系统的可靠性和性能。

Product data sheet

PUBLIC

Rev. 3.5 — 21 June 2010

112135 15 of 92

NXP Semiconductors

MFRC522

Contactless reader IC

8.1.4 I

C-bus interface

An I

C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus

interface to the host. The I

C-bus interface is implemented according to

NXP Semiconductors’ I

C-bus interface specification, rev. 2.1, January 2000. The

interface can only act in Slave mode. Therefore the MFRC522 does not implement clock

generation or access arbitration.

The MFRC522 can act either as a slave receiver or slave transmitter in Standard mode,

Fast mode and High-speed mode.

SDA is a bidirectional line connected to a positive supply voltage using a current source or

a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The

MFRC522 has a 3-state output stage to perform the wired-AND function. Data on the

C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to

400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.

If the I

C-bus interface is selected, spike suppression is activated on lines SCL and SDA

as defined in the I

C-bus interface specification.

See Table 155 on page 76

for timing requirements.

Table 14. Address byte 0 register; address MOSI

7 (MSB) 6 5 4 3 2 1 0 (LSB)

1 = read

0 = write

reserved address

Fig 11. I

C-bus interface

001aak59

MFRC522

SDA

SCL

I2C

ADR_[5:0]

PULL-UP

NETWORK

CONFIGURATION

WIRING

PULL-UP

NETWORK

MICROCONTROLLER

Product data sheet

PUBLIC

Rev. 3.5 — 21 June 2010

112135 18 of 92

NXP Semiconductors

MFRC522

Contactless reader IC

8.1.4.5 7-Bit addressing

During the I

C-bus address procedure, the first byte after the START condition is used to

determine which slave will be selected by the master.

Several address numbers are reserved. During device configuration, the designer must

ensure that collisions with these reserved addresses cannot occur. Check the I

C-bus

specification for a complete list of reserved addresses.

The I

C-bus address specification is dependent on the definition of pin EA. Immediately

after releasing pin NRSTPD or after a power-on reset, the device defines the I

C-bus

address according to pin EA.

If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by

NXP Semiconductors and set to 0101b for all MFRC522 devices. The remaining 3 bits

(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer

to prevent collisions with other I

C-bus devices.

If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins

according to Table 5 on page 8

. ADR_6 is always set to logic 0.

In both modes, the external address coding is latched immediately after releasing the

reset condition. Further changes at the used pins are not taken into consideration.

Depending on the external wiring, the I

C-bus address pins can be used for test signal

outputs.

8.1.4.6 Register write access

To write data from the host controller using the I

C-bus to a specific register in the

MFRC522 the following frame format must be used.

• The first byte of a frame indicates the device address according to the I

C-bus rules.

• The second byte indicates the register address followed by up to n-data bytes.

In one frame all data bytes are written to the same register address. This enables fast

FIFO buffer access. The Read/Write (R/W

) bit is set to logic 0.

Fig 16. First byte following the START procedure

001aak59

slave address

bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

MSB LSB

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