FPGA实现CAN总线控制：Verilog源代码详解

ENTITY can_ctrl IS
  port(
      clk   : in std_logic;
      reset : in std_logic;
      
          --15个io，还有一个中断io自己控制
      data                              :inout std_logic_vector(7 downto 0);
      ale                              :out std_logic:='0';
      nrd                              :out std_logic:='1';
      nwr                             :out std_logic:='1';
      ncs                             :out std_logic:='1';
      rst                            :out std_logic:='0';
      data_dir                         :out std_logic:='0';
          noe                             :out std_logic;
          --下面的是和你的控制逻辑交互的
      r_state_in                   :in std_logic;
      r_state_out                  :out std_logic;  
      w_state_in                   :in std_logic;
      w_state_out                  :out std_logic;    
      rw_addr               :in std_logic_vector(7 downto 0);
      rw_data_in            :in std_logic_vector(7 downto 0);
      rw_data_out           :out std_logic_vector(7 downto 0);
      );
END ENTITY can_ctrl;

ARCHITECTURE active OF can_ctrl IS
signal data_out             :std_logic_vector(7 downto 0);
signal data_in                     :std_logic_vector(7 downto 0);
signal data_out_en          :std_logic;
signal data_temp            :std_logic_vector(7 downto 0);

signal av_r_state_out,av_w_state_out : std_logic;
signal av_addr          :std_logic_vector(7 downto 0);

type states is(idle,read,write);
signal current_state:states;
signal next_state : states;
signal count :std_logic_vector(3 downto 0);

BEGIN 
        r_state_out <= av_r_state_out;
          w_state_out <= av_w_state_out;
        rst <= reset;
          data_in <= data;
          data <= data_out when data_out_en = '1' else (others => 'Z');
        
          process(clk,reset)
    begin
             if reset = '0' then
                       current_state <= idle;
             else
                       if rising_edge(clk) then
                         current_state <= next_state;
                       end if;
             end if; 
    end process;
    
          process(r_state_in,w_state_in,count)
            begin
                      case current_state is
                              when idle =>