"了解PCIE 4.0 Base 1.0规范及相关发展流程和修正信息"

PCIE4.0

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PCIE 4.0 Base 1.0规范是一份有关PCI Express（PCIE）4.0协议的技术规范文档。该规范的目的是为电子设备中的主机和外设提供一种高速数据传输接口，并提供有关通信协议和硬件设计的指导。第一部分介绍了该规范的背景和目的，并对PCIE 4.0协议的特性和优势进行了概述。 PCIE 4.0协议是PCIE技术的最新版本，采用了更高的数据传输速率和更好的性能。与之前的版本相比，PCIE 4.0的数据传输速率提高了两倍，达到了16 GT/s，同时还提供了更大的带宽和更低的延迟。第二部分是对PCIE 4.0协议的详细说明。该部分介绍了PCIE 4.0的物理和逻辑层规范，包括电信号的特性和传输方式，以及数据传输的编码和解码方法。此外，该部分还介绍了PCIE 4.0的链接和流控制机制，以及数据包的格式和传输流程。第三部分是关于PCIE 4.0的配置和管理。该部分介绍了PCIE 4.0设备的配置寄存器和控制寄存器的结构和功能，以及如何进行设备的初始化和配置。此外，该部分还介绍了PCIE 4.0的错误检测和纠正机制，以及电源管理和电源管理的特性和要求。第四部分是有关PCIE 4.0系统的设计和实施的指南。该部分介绍了PCIE 4.0的系统架构和拓扑结构，以及系统中PCIE 4.0设备和主机之间的连接和通信方式。此外，该部分还提供了有关PCIE 4.0设备的布局和布线规范的建议，以及如何进行电磁兼容性和干扰测试。第五部分是有关PCIE 4.0测试和验证的指导。该部分介绍了PCIE 4.0测试的方法和流程，包括电性测试、时序测试和功能测试。此外，该部分还介绍了PCIE 4.0设备的质量和可靠性评估的方法和标准。最后，该规范提供了一些关于PCIE 4.0的开放问题和未解决问题的说明。开放问题是指目前尚未解决或需要进一步讨论和研究的问题，而未解决问题是指已经被确认但尚未得到解决的问题。对于这些问题，规范建议读者要关注后续的修正和变更通知，并及时了解相关的发展和进展。需要注意的是，该规范中的错误和技术变更通知（ECN）的发布和更新流程与规范内容的开发和发布流程是分开进行的。因此，可能会存在正在进行中的错误和技术变更通知，并在其正常的流程中得到批准和发布，最终会在未来版本的规范中得到修正和更新。除了PCIE 4.0规范的基本内容，该规范还包含了从传统PCI、PCI-PM规范、PCI到PCI桥接和SR-规范中提取的一些材料。这些材料与PCIE 4.0规范的内容相关，并提供了对PCIE 4.0协议的更全面和深入的理解。总之，PCIE 4.0 Base 1.0规范是一份关于PCIE 4.0协议的详细技术规范文档，提供了PCIE 4.0协议的特性和优势的概述，以及对PCIE 4.0协议的物理、逻辑、配置、管理、设计和实施、测试和验证的详细说明和指导。同时，读者还需要关注规范中的开放问题和未解决问题，并及时了解相关的修正和更新。该规范还包含了一些与PCIE 4.0协议相关的材料，以提供更全面和深入的理解。

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PCI Express Base Specification, Rev. 4.0 Version 1.0

8.6.6 Common Refclk Rx Architecture (CC) .................................................................. 1100

8.6.7 Jitter Limits for Refclk Architectures .................................................................... 1103

8.6.8 Form Factor Requirements for RefClock Architectures ....................................... 1103

9 SINGLE ROOT I/O VIRTUALIZATION AND SHARING ...................................... 1106

9.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1106

9.1.1 PCI Technologies Interoperability ....................................................................... 1118

9.2 INITIALIZATION AND RESOURCE ALLOCATION .......................................................... 1119

9.2.1 SR-IOV Resource Discovery ................................................................................. 1119

9.2.2 Reset Mechanisms ................................................................................................. 1123

9.2.3 IOV Re-initialization and Reallocation ................................................................ 1124

9.2.4 VF Migration ........................................................................................................ 1124

9.3 CONFIGURATION ........................................................................................................ 1128

9.3.1 Overview ............................................................................................................... 1128

9.3.2 Configuration Space ............................................................................................. 1128

9.3.3 SR-IOV Extended Capability ................................................................................ 1128

9.3.4 PF/VF Configuration Space Header .................................................................... 1146

9.3.5 PCI Express Capability......................................................................................... 1150

9.3.6 PCI Standard Capabilities .................................................................................... 1156

9.3.7 PCI Express Extended Capabilities ...................................................................... 1157

9.4 ALL VFS ASSOCIATED WITH THE SAME PF SHALL REPORT THE SAME TIME

VALUES

.ERROR HANDLING .................................................................................................... 1169

9.4.1 Baseline Error Reporting ...................................................................................... 1169

9.4.2 Advanced Error Reporting .................................................................................... 1170

9.5 INTERRUPTS ............................................................................................................... 1175

9.5.1 Interrupt Mechanisms ........................................................................................... 1175

9.6 POWER MANAGEMENT ............................................................................................... 1176

9.6.1 VF Device Power Management States .................................................................. 1177

9.6.2 PF Device Power Management States .................................................................. 1178

9.6.3 Link Power Management State ............................................................................. 1178

9.6.4 VF Power Management Capability ...................................................................... 1178

9.6.5 VF EmergencyPower Reduction State .................................................................. 1179

10 ATS SPECIFICATION .................................................................................................. 1180

10.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1180

10.1.1 Address Translation Services (ATS) Overview ................................................. 1182

10.1.2 Page Request Interface Extension .................................................................... 1187

10.1.3 Process Address Space ID (PASID) ................................................................. 1189

10.2 ATS TRANSLATION SERVICES ................................................................................... 1190

10.2.1 Memory Requests with Address Type ............................................................... 1190

10.2.2 Translation Requests ......................................................................................... 1191

10.2.3 Translation Completion .................................................................................... 1194

10.2.4 Completions with Multiple Translations ........................................................... 1202

10.3 ATS INVALIDATION ................................................................................................... 1204

10.3.1 Invalidate Request ............................................................................................. 1204

10.3.2 Invalidate Completion ....................................................................................... 1205

10.3.3 Invalidate Completion Semantics ..................................................................... 1207

PCI Express Base Specification, Rev. 4.0 Version 1.0

10.3.4 Request Acceptance Rules................................................................................. 1208

10.3.5 Invalidate Flow Control .................................................................................... 1208

10.3.6 Invalidate Ordering Semantics ......................................................................... 1209

10.3.7 Implicit Invalidation Events .............................................................................. 1210

10.3.8 PASID TLP Prefix and Global Invalidate ........................................................ 1211

10.4 PAGE REQUEST SERVICES .......................................................................................... 1212

10.4.1 Page Request Message ...................................................................................... 1213

10.4.2 Page Request Group Response Message .......................................................... 1217

10.5 CONFIGURATION ........................................................................................................ 1219

10.5.1 ATS Extended Capability Structure .................................................................. 1219

10.5.2 Page Request Extended Capability Structure ................................................... 1222

A. ISOCHRONOUS APPLICATIONS ................................................................................. 1228

A.1. INTRODUCTION .......................................................................................................... 1228

A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ......................................... 1230

A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ........................... 1231

A.2.2. Isochronous Payload Size ................................................................................. 1232

A.2.3. Isochronous Bandwidth Allocation ................................................................... 1232

A.2.4. Isochronous Transaction Latency ..................................................................... 1233

A.2.5. An Example Illustrating Isochronous Parameters ............................................ 1234

A.3. ISOCHRONOUS TRANSACTION RULES ......................................................................... 1235

A.4. TRANSACTION ORDERING .......................................................................................... 1235

A.5. ISOCHRONOUS DATA COHERENCY ............................................................................. 1235

A.6. FLOW CONTROL ......................................................................................................... 1236

A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ..................................................... 1236

A.7.1. Isochronous Bandwidth of PCI Express Links.................................................. 1236

A.7.2. Isochronous Bandwidth of Endpoints ............................................................... 1236

A.7.3. Isochronous Bandwidth of Switches ................................................................. 1236

A.7.4. Isochronous Bandwidth of Root Complex......................................................... 1237

A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ................................................... 1237

A.8.1. An Endpoint as a Requester .............................................................................. 1237

A.8.2. An Endpoint as a Completer ............................................................................. 1237

A.8.3. Switches............................................................................................................. 1238

A.8.4. Root Complex .................................................................................................... 1239

B. SYMBOL ENCODING .................................................................................................... 1240

C. PHYSICAL LAYER APPENDIX .................................................................................... 1249

C.1. 8B/10B DATA SCRAMBLING EXAMPLE ....................................................................... 1249

C.2. 128B/130B DATA SCRAMBLING EXAMPLE ................................................................. 1255

D. REQUEST DEPENDENCIES .......................................................................................... 1258

E. ID-BASED ORDERING USAGE .................................................................................... 1261

E.1. INTRODUCTION .......................................................................................................... 1261

E.2. POTENTIAL BENEFITS WITH IDO USE ........................................................................ 1262

E.2.1. Benefits for MFD/RP Direct Connect ............................................................... 1262

E.2.2. Benefits for Switched Environments ................................................................. 1262

PCI Express Base Specification, Rev. 4.0 Version 1.0

E.2.3. Benefits for Integrated Endpoints ..................................................................... 1263

E.2.4. IDO Use in Conjunction with RO ..................................................................... 1263

E.3. WHEN TO USE IDO .................................................................................................... 1263

E.4. WHEN NOT TO USE IDO ............................................................................................ 1264

E.4.1. When Not to Use IDO with Endpoints .............................................................. 1264

E.4.2. When Not to Use IDO with Root Ports ............................................................. 1264

E.5. SOFTWARE CONTROL OF IDO USE ............................................................................. 1265

E.5.1. Software Control of Endpoint IDO Use ............................................................ 1265

E.5.2. Software Control of Root Port IDO Use ........................................................... 1266

F. MESSAGE CODE USAGE .............................................................................................. 1267

G. PROTOCOL MULTIPLEXING ................................................................................... 1269

G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS ................................. 1272

G.2. PMUX PACKETS ........................................................................................................ 1277

G.3. PMUX PACKET LAYOUT ........................................................................................... 1278

G.3.1. PMUX Packet Layout for 8b/10b Encoding ..................................................... 1278

G.3.2. PMUX Packet Layout at 128b/130b Encoding ................................................. 1280

G.4. PMUX CONTROL ....................................................................................................... 1283

G.5. PMUX EXTENDED CAPABILITY ................................................................................. 1283

G.5.1. PCI Express Extended Header (Offset 00h) ..................................................... 1284

G.5.2. PMUX Capability Register (Offset 04h) ........................................................... 1285

G.5.3. PMUX Control Register (Offset 08h) ............................................................... 1286

G.5.4. PMUX Status Register (Offset 0Ch) ................................................................. 1288

G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) ........................................... 1291

H. FLOW CONTROL UPDATE LATENCY AND ACK UPDATE LATENCY

CALCULATIONS .................................................................................................................... 1293

H.1. FLOW CONTROL UPDATE LATENCY ........................................................................... 1293

H.2. ACK LATENCY ........................................................................................................... 1295

ACKNOWLEDGEMENTS ...................................................................................................... 1298

PCI Express Base Specification, Rev. 4.0 Version 1.0

Figures

FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 58

FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 59

FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 63

FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 65

FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 66

FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 71

FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 74

FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 75

FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 76

FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 77

FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 82

FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 84

FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 84

FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 86

FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 86

FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 87

FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 90

FIGURE 2-13: TRANSACTION ID .................................................................................................... 90

FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 97

FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ...................... 100

FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ...................... 100

FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS ............................................ 101

FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ...................... 102

FIGURE 2-19: TPH TLP PREFIX .................................................................................................. 103

FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ........................................... 103

FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ........................................... 104

FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ....................... 104

FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ... 105

FIGURE 2-24: MESSAGE REQUEST HEADER ................................................................................ 107

FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 117

FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 118

FIGURE 2-27: LN MESSAGE ......................................................................................................... 120

FIGURE 2-28: DRS MESSAGE ...................................................................................................... 121

FIGURE 2-29: FRS MESSAGE ...................................................................................................... 122

FIGURE 2-30: HIERARCHY ID MESSAGE ..................................................................................... 124

FIGURE 2-31: LTR MESSAGE ...................................................................................................... 126

FIGURE 2-32: OBFF MESSAGE ................................................................................................... 127

FIGURE 2-33: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 128

FIGURE 2-34: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 128

FIGURE 2-35: COMPLETION HEADER FORMAT ............................................................................ 129

FIGURE 2-36: (NON-ARI) COMPLETER ID .................................................................................. 130

FIGURE 2-37: ARI COMPLETER ID .............................................................................................. 130

FIGURE 2-38: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 137

FIGURE 2-39: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 139

PCI Express Base Specification, Rev. 4.0 Version 1.0

FIGURE 2-40: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 144

FIGURE 2-41: EXAMPLE COMPLETION DATA WHEN SOME BYTE ENABLES ARE 0B ..................... 148

FIGURE 2-42: VIRTUAL CHANNEL CONCEPT – AN ILLUSTRATION .............................................. 160

FIGURE 2-43: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM FLOW) ............. 161

FIGURE 2-44: AN EXAMPLE OF TC/VC CONFIGURATIONS .......................................................... 163

FIGURE 2-45: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ..................... 164

FIGURE 2-46: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY

PROTECTION ........................................................................................................................ 181

FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 189

FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .................................. 192

FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED

FRAMING ............................................................................................................................. 200

FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 203

FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK ....................................... 205

FIGURE 3-6: NOP DATA LINK LAYER PACKET FORMAT ............................................................. 205

FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 205

FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 206

FIGURE 3-9: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC ............................................ 206

FIGURE 3-10: PM DATA LINK LAYER PACKET FORMAT ............................................................. 206

FIGURE 3-11: VENDOR-SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 206

FIGURE 3-12: DATA LINK FEATURE DLLP ................................................................................. 206

FIGURE 3-13: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 208

FIGURE 3-14: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 208

FIGURE 3-15: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS

............................................................................................................................................. 211

FIGURE 3-16: CALCULATION OF LCRC ...................................................................................... 213

FIGURE 3-17: RECEIVED DLLP ERROR CHECK FLOWCHART ...................................................... 219

FIGURE 3-18: ACK/NAK DLLP PROCESSING FLOWCHART .......................................................... 220

FIGURE 3-19: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 224

FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER .......................................... 229

FIGURE 4-2: CHARACTER TO SYMBOL MAPPING ......................................................................... 230

FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 231

FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 231

FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 234

FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 235

FIGURE 4-7: FRAMED TLP ON A X1 LINK .................................................................................... 235

FIGURE 4-8: FRAMED TLP ON A X2 LINK .................................................................................... 236

FIGURE 4-9: FRAMED TLP ON A X4 LINK .................................................................................... 236

FIGURE 4-10: LFSR WITH 8B/10B SCRAMBLING POLYNOMIAL ................................................... 238

FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A

BLOCK ................................................................................................................................. 239

FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 240

FIGURE 4-13: LAYOUT OF FRAMING TOKENS .............................................................................. 243

FIGURE 4-14: TLP AND DLLP LAYOUT ...................................................................................... 245

FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 245

FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS ............................. 246

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