GM8136S/GM8135S H.264 IP-CAM SoC Data Sheet: MPEG4/JPEG Codec Features & Specifications

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GM8136是一款专为视频编码加速而设计的硬件解码器，它集成了MPEG4和JPEG编解码引擎，专注于处理那些计算密集型任务，如运动估计、离散余弦变换（DCT）、量化/逆量化、预测编码以及VLC/VLD计算。这款芯片主要应用于H.264编码的IP摄像头SoC（System-on-Chip）中，支持多种分辨率标准，包括子QCIF、QCIF、CIF、VGA、D1和720p，步长为16像素。其特性包括： 1. 兼容性：符合MPEG4简单profile L0~L3标准，支持各种分辨率，以及JPEG基本标准。 2. 硬件引擎：内置硬件模块用于运动估计/补偿、DCT/IDCT、量化/逆量化、AC/DC预测和可变长度编码/解码。 3. 内存管理：配备本地内存控制器，协同CPU、MPEG4/JPEG解码器和DMA主控器共享存储资源。 4. 数据传输：通过DMA控制器实现系统内存与本地内存之间的高效数据交换。 5. 节能设计：支持自动电源管理，降低功耗。 6. 搜索范围：运动估计搜索范围可达-16到+15.5（可选-32到+31），精度达到半像素级别。 7. 短视频头支持：支持H.263基础版本的短视频头格式。 8. 量化方法：支持H.263/MPEG/JPEG的量化方法。修订历史记录显示，GM8136S/GM8135SH.264IP-CAMSOC的数据表在2014年多次更新，增加了功能概述、修改了某些表格的内容，并对封装格式进行了相应调整。同时强调了版权信息和注意事项，指出产品不适用于可能导致人身伤害或死亡的植入或支撑应用，并声明所有信息可能随时变更，不构成产品规格或保修承诺。 GM8136是一款高度集成且性能强大的视频编码加速器，针对视频处理任务进行了优化设计，是构建高效能视频处理系统的重要组件。开发者在使用时需关注其最新的规格和功能更改，以确保最佳性能和兼容性。

GM8136S/GM8135S Data Sheet

www.grain-media.com

xii

Table 6-1. Summary of DDR Controller Registers ............................................................................. 179

Table 6-2. Memory Controller Configuration Register (Offset = 0x00) ............................................... 182

Table 6-3. Memory Controller State Control Register (Offset = 0x04) ............................................... 185

Table 6-4. Mode Register Set Value Register of MR and EMR (Offset = 0x08) ................................ 188

Table 6-5. Mode Register Set Value Register of EMR 2 and EMR 3 (Offset = 0x0C) ....................... 189

Table 6-6. External Rank0/1 Register (Offset = 0x10) ....................................................................... 189

Table 6-7. Timing Parameter 0 Register (Offset = 0x14) ................................................................... 191

Table 6-8. Timing Parameter 1 Register (Offset = 0x18) ................................................................... 193

Table 6-9. Timing Parameter 2 Register (Offset = 0x1C) .................................................................. 196

Table 6-10. Command and Data Block Control Register (Offset = 0x20) ............................................ 198

Table 6-11. Read Path DLL Delay Tuning Register (Offset = 0x24) .................................................... 200

Table 6-12. COMPBLK Control Register (Offset = 0x28)..................................................................... 200

Table 6-13. Automatic Power-down/Self-refresh Control Register (Offset = 0x2C) ............................. 201

Table 6-14. Channel Arbitration Setup Register (Offset = 0x30) ......................................................... 202

Table 6-15. Channel Arbiter Grant Count Register - A (Offset = 0x34) ............................................... 203

Table 6-16. Write/Read Data Timing Control Register (Offset = 0x3C) ............................................... 206

Table 6-17. Command Flush Control Register (Offset = 0x40) ............................................................ 208

Table 6-18. Command Flush Status Register (Offset = 0x44) ............................................................. 208

Table 6-19. AHB SPLIT Control Register1 (Offset = 0x48) .................................................................. 209

Table 6-20. Update Control Register (Offset = 0x4C) .......................................................................... 210

Table 6-21. User Define Register (Offset = 0x5C) ............................................................................... 210

Table 6-22. Write-leveling Control Register (Offset = 0x60) (Only for DDR3 Mode) ........................... 211

Table 6-23. Write-leveling Byte 3 ~ Byte 0 Control Register (Offset = 0x68) (Only for DDR3 Mode).. 212

Table 6-24. MISC Control Register 1 (Offset = 0x6C) (Only for DDR3 Mode) .................................... 213

Table 6-25. Read-leveling Control Register (Offset = 0x70) (Only for DDR3 Mode) ........................... 213

Table 6-26. msdly Byte Control Register (Offset = 0x74)..................................................................... 214

Table 6-27. wrdllsel Control Register (Offset = 0x78) .......................................................................... 215

Table 6-28. Traffic Monitor Clock Cycle Register (Offset = 0x7C) ....................................................... 215

Table 6-29. Command Count Register for Channel 0 (Offset = 0x80) ................................................. 215

Table 6-30. Command Count Register for Channel 1 (Offset = 0x84) ................................................. 216

Table 6-31. Command Count Register for Channel 2 (Offset = 0x88) ................................................. 216

Table 6-32. Command Count Register for Channel 3 (Offset = 0x8C) ................................................ 216

Table 6-33. AHB INCR Read Prefetch Length 1 (Offset = 0xA0) ........................................................ 217

Table 6-34. Initialization of Waiting Cycle Count 1 (Offset = 0xA8) ..................................................... 217

GM8136S/GM8135S Data Sheet

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xiii

Table 6-35. Initialization of Waiting Cycle Count 2 (Offset = 0xAC) ..................................................... 218

Table 6-36. QoS Control Register (Offset = 0xB0) ............................................................................... 218

Table 6-37. QoS Command Control Register A (Offset = 0xB4) ......................................................... 219

Table 6-38. QoS Command Control Register C (Offset = 0xBC) ......................................................... 220

Table 6-39. Channel Arbitration Setup Register B (Offset = 0xC4) ..................................................... 221

Table 6-40. Channel Arbiter Grant Control Register C (Offset = 0xC8) ............................................... 222

Table 6-41. Debug Address (Offset = 0xD0) ........................................................................................ 224

Table 6-42. Debug Address Mask (Offset = 0xD4) .............................................................................. 224

Table 6-43. Debug Write Data (Offset = 0xD8) .................................................................................... 224

Table 6-44. Debug Write Data Mask (Offset = 0xDC) .......................................................................... 224

Table 6-45. Debug Master Control (Offset = 0xE0) .............................................................................. 225

Table 6-46. Debug Access Control (Offset = 0xE4) ............................................................................. 225

Table 6-47. Debug Policy Control (Offset = 0xE8) ............................................................................... 226

Table 6-48. Debug Control (Offset = 0xEC) ......................................................................................... 226

Table 6-49. Debug Address Status (Offset = 0xF0) ............................................................................. 226

Table 6-50. Debug Write Data Status (Offset = 0xF4) ......................................................................... 227

Table 6-51. Debug Master Status (Offset = 0xF8) ............................................................................... 227

Table 6-52. Debug Access Status (Offset = 0xFC) .............................................................................. 227

Table 6-55. MA Table (AMTSEL = 00) in 8bit DDR3/DDR2 Mode ...................................................... 230

Table 6-56. MA Table (AMTSEL = 00) in 16bit DDR3/DDR2 Mode .................................................... 231

Table 6-57. MA Table (AMTSEL = 01) in 8bit DDR3/DDR2 Mode ...................................................... 232

Table 6-58. MA Table (AMTSEL = 01) in 16bit DDR3/DDR2 Mode .................................................... 233

Table 6-59. MA Table (AMTSEL = 10) in 16bit DDR3/DDR2 Mode .................................................... 235

Table 6-60. Summary of Control Registers .......................................................................................... 241

Table 6-61. Command Queue First Word (Address = 0x0000) ........................................................... 242

Table 6-62. Command Queue Second Word (Address = 0x00004) .................................................... 242

Table 6-63. Command Queue Third Word (Address = 0x0008) .......................................................... 244

Table 6-64. Command Queue Fourth Word (Address = 0x000C) ....................................................... 244

Table 6-65. Control Register (Address = 0x0010) ................................................................................ 245

Table 6-66. AC Timing Register (Address = 0x0014) .......................................................................... 246

Table 6-67. Status Register (Address = 0x0018) ................................................................................. 246

Table 6-68. Interrupt Control Register (Address = 0x0020) ................................................................. 247

Table 6-69. RXFIFO Trigger Level ....................................................................................................... 247

Table 6-70. TXFIFO Trigger Level ....................................................................................................... 247

GM8136S/GM8135S Data Sheet

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xiv

Table 6-71. Interrupt Status Register (Address = 0x0024) .................................................................. 248

Table 6-72. SPI Read Status Register (Address = 0x0028) ................................................................ 248

Table 6-73. Revision Register (Address = 0x0050) ............................................................................. 248

Table 6-74. Feature Register (Address = 0x0054) ............................................................................... 248

Table 6-75. Data Port Register (Address = 0x0100) ............................................................................ 249

Table 7-1. Mapping of Usual Special-purpose Registers ................................................................... 262

Table 7-2. Definition of Register Abbreviation .................................................................................... 265

Table 7-3. CSIRX Registers ............................................................................................................... 266

Table 7-4. Vendor ID Register (VIDR, Offset = 0x00) ........................................................................ 267

Table 7-5. Device ID Register (DIDR, Offset = 0x01) ........................................................................ 267

Table 7-6. Control Register (CR, Offset = 0x04) ................................................................................ 268

Table 7-7. DPI VSync Control Register (VSCR, Offset = 0x05) ......................................................... 269

Table 7-8. Extended Control Register (ECR, Offset = 0x06) ............................................................. 270

Table 7-9. Timer Count Number Lower Register (TCNLR, Offset = 0x08) ........................................ 270

Table 7-10. Timer Count Number Higher Register (TCNHR, Offset = 0x09) ....................................... 270

Table 7-11. HS RX Timeout Value Register (HRTVR, Offset = 0x0A) ................................................. 271

Table 7-12. Initialization Timer Lower Register (ITLR, Offset = 0x12) ................................................. 271

Table 7-13. Initialization Timer Higher Register (ITHR, Offset = 0x13) ................................................ 272

Table 7-14. DPI VC0 VSync Timing Register (VSTR0, Offset = 0x14) ................................................ 272

Table 7-15. DPI VC0 HSync Timing Register (HSTR0, Offset = 0x15) ............................................... 272

Table 7-16. DPI Mapping Control Register (MCR, Offset = 0x1C) ...................................................... 273

Table 7-17. DPI VSync Timing Extended Register 0 (VSTER0, Offset = 0x1E) .................................. 273

Table 7-18. VC0 Horizontal Pixel Number Lower Register (HPNLR0, Offset = 0x20) ......................... 274

Table 7-19. VC0 Horizontal Pixel Number Higher Register (HPNHR0, Offset = 0x21) ....................... 274

Table 7-20. PPI Enable Control Register (PECR, Offset = 0x28) ........................................................ 274

Table 7-21. Data Lane Mapping Register 0 (DLMR0, Offset = 0x2A) .................................................. 275

Table 7-22. CSI Error Report Register 0 (CSIERR0, Offset = 0x30) ................................................... 275

Table 7-23. CSI Error Report Register 1 (CSIERR1, Offset = 0x31) ................................................... 276

Table 7-24. Interrupt Status Register (INTSTS, Offset = 0x33) ........................................................... 277

Table 7-25. Escape Mode and Stop State Register 0 (ESR0, Offset = 0x34) ..................................... 278

Table 7-26. Escape Mode and Stop State Register 1 (ESR1, Offset = 0x35) ..................................... 278

Table 7-27. DPI VC0 Status Register (DPISR0, Offset = 0x38) .......................................................... 279

Table 7-28. Interrupt Enable Register (INTER, Offset = 0x3C) ............................................................ 280

Table 7-29. CSIRX Feature Register 0 (FFR0, Offset = 0x40) ............................................................ 281

GM8136S/GM8135S Data Sheet

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Table 7-30. VC0 DPCM Register (DPCMR0, Offset = 0x48) ............................................................... 281

Table 7-31. CSIRX Revision Register (FRR, Offset = 0x4C) ............................................................... 282

Table 7-32. Pixel FIFO Threshold Register (PFTR0, Offset = 0x50) ................................................... 283

Table 7-33. CSIRX PHY Control Register 0a (PHYCTRL0a, Offset = 0x60) ....................................... 283

Table 7-34. CSIRX PHY Control Register 0b (PHYCTRL0b, Offset = 0x61) ....................................... 283

Table 7-35. CSIRX PHY Control Register 0c (PHYCTRL0c, Offset = 0x62) ....................................... 284

Table 7-36. CSIRX PHY Control Register 0d (PHYCTRL0d, Offset = 0x63) ....................................... 284

Table 7-37. CSIRX PHY Control Register 1a (PHYCTRL1a, Offset = 0x64) ....................................... 284

Table 7-38. CSIRX PHY Control Register 1b (PHYCTRL1b, Offset = 0x65) ....................................... 284

Table 7-39. CSIRX PHY Control Register 1c (PHYCTRL1c, Offset = 0x66) ....................................... 284

Table 7-40. CSIRX PHY Control Register 1d (PHYCTRL1d, Offset = 0x67) ....................................... 285

Table 7-41. CSIRX PHY Control Register 2a (PHYCTRL2a, Offset = 0x68) ....................................... 285

Table 7-42. RxDataHsSettleCnt ........................................................................................................... 285

Table 7-43. CSIRX PHY Control Register 2b (PHYCTRL2b, Offset = 0x69) ....................................... 286

Table 7-44. CSIRX PHY Control Register 2c (PHYCTRL2c, Offset = 0x6A) ....................................... 286

Table 7-45. CSIRX PHY Control Register 2d (PHYCTRL2d, Offset = 0x6B) ...................................... 286

Table 7-46. CSIRX PHY Control Register 3a (PHYCTRL3a, Offset = 0x6C) ...................................... 286

Table 7-47. CSIRX PHY Control Register 3b (PHYCTRL3b, Offset = 0x6D) ...................................... 287

Table 7-48. CSIRX PHY Control Register 3c (PHYCTRL3c, Offset = 0x6E) ....................................... 287

Table 7-49. CSIRX PHY Control Register 3d (PHYCTRL3d, Offset = 0x6F)....................................... 287

Table 7-50. Frame Control Wrap Register for VC0 (FCWR0, Offset = 0x80) ...................................... 288

Table 7-51. Frame Enable Register for VC0 (FER0, Offset = 0x81) .................................................... 288

Table 7-52. Frame Number Lower Register for VC0 (FNLR0, Offset = 0x88) ..................................... 288

Table 7-53. Frame Number Higher Register for VC0 (FNHR0, Offset = 0x89) ................................... 289

Table 7-54. DPI Built-in Pattern Generator Lower Register for VC0 (BPGLR0, Offset = 0x90) .......... 289

Table 7-55. DPI Built-in Pattern Generator Higher Register for VC0 (BPGHR0, Offset = 0x91) ......... 289

Table 7-56. Summary of subLVDS Controller Registers ...................................................................... 292

Table 7-57. subLVDS_CTRL_Reg (Offset = 0x00) .............................................................................. 293

Table 7-58. subLVDS_SIZE_Reg (Offset = 0x04) ............................................................................... 295

Table 7-59. subLVDS_SYNC_Reg (Offset = 0x08) ............................................................................. 295

Table 7-60. subLVDS_INTR_Reg (Offset = 0x20) ............................................................................... 296

Table 7-61. subLVDS_VER_Reg (Offset = 0x80) ................................................................................ 296

Table 7-62. subLVDS_STATUS_Reg0 (Offset = 0x84) ....................................................................... 296

Table 7-63. subLVDS_STATUS_Reg1 (Offset = 0x88) ....................................................................... 297

GM8136S/GM8135S Data Sheet

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xvi

Table 7-64. subLVDS_STATUS_Reg2 (Offset = 0x8C)....................................................................... 297

Table 7-65. subLVDS_DEBUG_Reg0 (Offset = 0xA0) ........................................................................ 297

Table 7-66. subLVDS_DEBUG_Reg1 (Offset = 0xA4) ........................................................................ 297

Table 7-67. subLVDS_DEBUG_Reg2 (Offset = 0xA8) ........................................................................ 298

Table 7-68. subLVDS_DEBUG_Reg3 (Offset = 0xAC)........................................................................ 298

Table 7-69. subLVDS_DEBUG_Reg4 (Offset = 0xB0) ........................................................................ 298

Table 7-70. subLVDS_DEBUG_Reg5 (Offset = 0xB4) ........................................................................ 298

Table 7-71. subLVDS_DEBUG_Reg6 (Offset = 0xB8) ........................................................................ 299

Table 7-72. subLVDS_DEBUG_Reg7 (Offset = 0xBC)........................................................................ 299

Table 8-1. Summary of LCD Controller Registers .............................................................................. 303

Table 8-2. LCD Function Enable Parameters (Address = 0x0000) .................................................... 306

Table 8-3. LCD Panel Pixel Parameters (Address = 0x0004) ............................................................ 308

Table 8-4. LCD Interrupt Enable Mask Parameters (Address = 0x0008) .......................................... 311

Table 8-5. LCD Interrupt Status Clear Parameters (Address = 0x000C) ........................................... 311

Table 8-6. LCD Interrupt Status Parameters (Address = 0x0010) ..................................................... 312

Table 8-7. Frame Buffer Parameters (Address = 0x0014) ................................................................. 312

Table 8-8. Image0 Frame Base Address (Address = 0x0018) ........................................................... 313

Table 8-9. Image1 Frame Base Address (Address = 0x0024) ........................................................... 313

Table 8-10. PatGen Pattern Bar Distance Parameters (Address = 0x0048) ....................................... 314

Table 8-11. FIFO Threshold Control Parameters (Address = 0x004C) ............................................... 314

Table 8-12. Bus Bandwidth Control Parameters (Address = 0x0050) ................................................. 315

Table 8-13. Revision Registers (Address = 0x0058)............................................................................ 316

Table 8-14. VBI Base Address (Address = 0x005C) ............................................................................ 316

Table 8-15. FIFO Threshold Control Parameters (Address = 0x0060) ................................................ 316

Table 8-16. LCD Horizontal Timing Control Parameters (Address = 0x0100) ..................................... 317

Table 8-17. LCD Vertical Timing Control Parameters (Address = 0x0104) ......................................... 318

Table 8-18. LCD Vertical Back Porch Parameters (Address = 0x0108) .............................................. 318

Table 8-19. LCD Polarity Control Parameters (Address = 0x010C) .................................................... 318

Table 8-20. LCD TV Parameter 0 (Address = 0x0204) ........................................................................ 320

Table 8-21. TV Parameter 1 (Address = 0x0204) ................................................................................ 322

Table 8-22. TV Field Polarity Parameter 2 (Address = 0x020C) .......................................................... 322

Table 8-23. TV Vertical Blank Parameter 3 (Address = 0x0210 .......................................................... 322

Table 8-24. TV Vertical Blank Parameter 4 (Address = 0x0214) ......................................................... 323

Table 8-25. TV Vertical Active Parameter 5 (Address = 0x0218) ........................................................ 323

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