Armv7-a参考手册_dxf参考手册

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Preface

Using this manual

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Using this manual

The information in this manual is organized into parts, as described in this section.

Part A, Application Level Architecture

Part A describes the application level view of the architecture. It contains the following chapters:

Chapter A1 Introduction to the ARM Architecture

Gives an overview of the ARM architecture, and the ARM and Thumb instruction sets.

Chapter A2 Application Level Programmers’ Model

Describes the application level view of the ARM programmers’ model, including the application

level view of the Advanced SIMD and Floating-point Extensions. It describes the types of values

that ARM instructions operate on, the ARM core registers that contain those values, and the

Application Program Status Register.

Chapter A3 Application Level Memory Model

Describes the application level view of the memory model, including the ARM memory types and

attributes, and memory access control.

Chapter A4 The Instruction Sets

Describes the range of instructions available in the ARM, Thumb, Advanced SIMD, and VFP

instruction sets. It also contains some details of instruction operation that are common to several

instructions.

Chapter A5 ARM Instruction Set Encoding

Describes the encoding of the ARM instruction set.

Chapter A6 Thumb Instruction Set Encoding

Describes the encoding of the Thumb instruction set.

Chapter A7 Advanced SIMD and Floating-point Instruction Encoding

Describes the encoding of the Advanced SIMD and Floating-point Extension (VFP) instruction sets.

Chapter A8 Instruction Descriptions

Gives a full description of every instruction available in the Thumb, ARM, Advanced SIMD, and

Floating-point Extension instruction sets, with the exception of information only relevant to

execution with some level of privilege.

Chapter A9 The ThumbEE Instruction Set

Gives a full description of the Thumb Execution Environment variant of the Thumb instruction set.

This means it describes the ThumbEE instruction set.

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Part B, System Level Architecture

Part B describes the system level view of the architecture. It contains the following chapters:

Chapter B1 System Level Programmers’ Model

Describes the system level view of the programmers’ model.

Chapter B2 Common Memory System Architecture Features

Describes the system level view of the memory model features that are common to all memory

systems.

Chapter B3 Virtual Memory System Architecture (VMSA)

Describes the system level view of the Virtual Memory System Architecture (VMSA) that is part of

all ARMv7-A implementations. This chapter includes a description of the organization and general

properties of the system control registers in a VMSA implementation.

Chapter B4 System Control Registers in a VMSA implementation

Describes all of the system control registers in VMSA implementation, including the registers that

are part of the

OPTIONAL extensions to a VMSA implementation. The registers are described in

alphabetical order.

Chapter B5 Protected Memory System Architecture (PMSA)

Describes the system level view of the Protected Memory System Architecture (PMSA) that is part

of all ARMv7-R implementations. This chapter includes a description of the organization and

general properties of the system control registers in a PMSA implementation.

Chapter B6 System Control Registers in a PMSA implementation

Describes all of the system control registers in PMSA implementation, including the registers that

are part of the

OPTIONAL extensions to a PMSA implementation. The registers are described in

alphabetical order.

Chapter B7 The CPUID Identification Scheme

Describes the CPUID scheme. This provides registers that identify the architecture version and

many features of the processor implementation. This chapter also describes the registers that

identify the implemented Advanced SIMD and VFP features, if any.

Chapter B8 The Generic Timer

Describes the

OPTIONAL Generic Timer architecture extension.

Chapter B9 System Instructions

Provides detailed reference information about system instructions, and more information about

instructions that behave differently when executed with some level of privilege.

Part C, Debug Architecture

Part C describes the Debug architecture. It contains the following chapters:

Chapter C1 Introduction to the ARM Debug Architecture

Introduces the Debug architecture, defining the scope of this part of the manual.

Chapter C2 Invasive Debug Authentication

Describes the authentication of invasive debug.

Chapter C3 Debug Events

Describes the debug events.

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Chapter C4 Debug Exceptions

Describes the debug exceptions that handle debug events when the processor is configured for

Monitor debug-mode.

Chapter C5 Debug State

Describes Debug state that is entered if a debug event occurs when the processor is configured for

Halting debug-mode.

Chapter C6 Debug Register Interfaces

Describes the permitted debug register interfaces and the options for their implementation.

Chapter C7 Debug Reset and Powerdown Support

Describes the reset and powerdown support in the Debug architecture, including support for debug

over powerdown.

Chapter C8 The Debug Communications Channel and Instruction Transfer Register

Describes the Debug Communication Channel (DCC) and Instruction Transfer Register (ITR), and

how an external debugger uses these features to communicate with the debug logic.

Chapter C9 Non-invasive Debug Authentication

Describes the authentication of non-invasive debug.

Chapter C10 Sample-based Profiling

Describes sample-based profiling, that provides sampling of the program counter.

Chapter C11 The Debug Registers

Describes the debug registers.

Chapter C12 The Performance Monitors Extension

Describes the

OPTIONAL Performance Monitors Extension.

Part D, Appendixes

This manual contains the following appendixes:

Appendix D1 Recommended External Debug Interface

Describes the recommended external interface to the ARM debug architecture.

Note

This description is not part of the ARM architecture specification. It is included here as

supplementary information, for the convenience of developers and users who might require this

information.

Appendix D2 Recommended Memory-mapped and External Debug Interfaces for the Performance Monitors

Describes the recommended external interfaces to the Performance Monitors Extension.

Note

This description is not part of the ARM architecture specification. It is included here as

supplementary information, for the convenience of developers and users who might require this

information.

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Appendix D3 Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION

DEFINED Events

Gives the ARM recommendations for the use of the event numbers in the

IMPLEMENTATION

DEFINED event number space.

Note

This description is not part of the ARM architecture specification. It is included here as

supplementary information, for the convenience of developers and users who might require this

information.

Appendix D4 Example OS Save and Restore Sequences for External Debug Over Powerdown

Gives software examples that perform the OS Save and Restore sequences, for v7 Debug and v7.1

Debug implementations.

Note

Chapter C7 Debug Reset and Powerdown Support describes the OS Save and Restore mechanism,

for both v7 Debug and v7.1 Debug.

Appendix D5 System Level Implementation of the Generic Timer

Contains the ARM Generic Timer architecture specification for the memory-mapped interface to

the Generic Timer.

Note

This description is not part of the ARM architecture specification. It is included here as

supplementary information, for the convenience of developers and users who might require this

information.

Appendix D6 Common VFP Subarchitecture Specification

Defines version 2 of the Common VFP Subarchitecture.

Note

This specification is not part of the ARM architecture specification. This sub-architectural

information is included here as supplementary information, for the convenience of developers and

users who might require this information.

Appendix D7 Barrier Litmus Tests

Gives examples of the use of the barrier instructions provided by the ARMv7 architecture.

Note

These examples are not part of the ARM architecture specification. They are included here as

supplementary information, for the convenience of developers and users who might require this

information.

Appendix D8 Legacy Instruction Mnemonics

Describes the legacy mnemonics and their Unified Assembler Language equivalents.

Appendix D9 Deprecated and Obsolete Features

Lists the deprecated architectural features, with references to their descriptions in parts A to C of

the manual.

Appendix D10 Fast Context Switch Extension (FCSE)

Describes the Fast Context Switch Extension (FCSE). See the appendix for information about the

status of this in different versions of the ARM architecture.

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