Spartan-3 Generation配置用户指南

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"Spartan-3 Generation332 - Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families Configuration User Guide" Spartan-3系列是Xilinx公司推出的一系列现场可编程门阵列（FPGA），主要包括Extended Spartan-3A、Spartan-3E和Spartan-3 FPGA家族。这些器件提供了丰富的数字信号处理和嵌入式系统设计解决方案，适用于广泛的电子应用领域，如通信、工业控制、消费电子和教育等。用户指南《Spartan-3 Generation Configuration User Guide》（UG332 v1.5，2009年3月16日发布）旨在帮助开发者充分利用这些FPGA进行设计。文档涵盖了配置过程、设计流程以及如何在Spartan-3 FPGA上实现不同功能的核心（IP核）。 IP核（ Intellectual Property Core）是在硬件描述语言（如VHDL或Verilog）中实现的预定义功能模块，可以是通用的，如UART（通用异步接收发送器）。UART是一种广泛用于设备间串行通信的标准接口，允许数据以比特流的形式在两个设备之间传输。在FPGA设计中，集成UART IP核可以帮助开发者快速构建通信系统。该用户指南详细介绍了如何在Spartan-3 FPGA中配置和使用这些IP核，包括UART，以实现高效、可靠的设计。配置过程可能涉及编程、时序分析、功耗优化以及与外部存储器或处理器的接口设计。此外，文档还可能涵盖错误检查、故障排查和最佳实践，以确保设计的正确性和稳定性。 Xilinx提供此文档供开发者在开发与Xilinx硬件设备协同工作的设计时使用，但对文档的复制、分发、发布、下载、展示、发布或以任何方式传输均需获得Xilinx的书面许可。同时，Xilinx明确声明不对因使用该文档产生的任何责任负责，并保留在任何时候不经通知修改文档的权利。尽管Xilinx不承担修正文档中任何错误的义务，但在提供技术支持或协助时，可能会告知用户有关错误的纠正或更新。《Spartan-3 Generation Configuration User Guide》是开发人员进行Spartan-3 FPGA设计的重要参考资料，它包含了必要的配置步骤、IP核集成方法以及相应的合规使用条款，对于理解和利用Spartan-3系列FPGA实现复杂系统设计至关重要。

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Figure 3-13: Generate PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 3-14: Program Platform Flash PROM using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 3-15: iMPACT Automatically Detects JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 3-16: Bypass Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 3-17: Select the Platform Flash Programming File . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 3-18: Program the Platform Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 3-19: PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Chapter 4: Master SPI Mode

Figure 4-1: SPI Flash Configuration Interface for M25P-compatible Devices . . . . . . . . 102

Figure 4-2: SPI Flash Configuration Interface for Atmel DataFlash Devices. . . . . . . . . 103

Figure 4-3: SPI Flash PROM/FPGA Power-On Timing if 3.3V

Supply is Last in Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 4-4: If Not Using SPI after Configuration, Drive CSO_B Pin High. . . . . . . . . . . 116

Figure 4-5: Using the SPI Flash Interface After Configuration . . . . . . . . . . . . . . . . . . . . . 117

Figure 4-6: Daisy Chaining from SPI Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 4-7: Multiple, Identical FPGAs Programmed with the Same Bitstream . . . . . . . 120

Figure 4-8: Using FPGA’s JTAG Test Chain to Program Attached SPI Flash . . . . . . . . 125

Figure 4-9: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . . 126

Figure 4-10: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 4-11: Set Options for a 3rd-Party SPI PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-12: Select SPI PROM Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-13: Review PROM Formatting Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 4-14: Add FPGA Configuration Bitstream File(s) . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 4-15: Generate PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 4-16: iMPACT Supports Direct Programming for SPI Serial Flash Memories. 131

Figure 4-17: Select a Previously-formatted PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-18: Select a Supported SPI Flash Memory Device. . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-19: Directly Program Supported SPI Flash PROM.. . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-20: SPI PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-21: Indirect Programming Method Uses JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 4-22: Select the FPGA Bitstream File and Enable SPI Programming . . . . . . . . . 135

Figure 4-23: iMPACT Uses the JTAG Clock Input TCK for Startup Clock when

Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-24: Select the SPI PROM Programming FIle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-25: Select SPI Flash PROM Type

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-26: Bypass the Platform Flash PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 4-27: iMPACT Presents JTAG Chain, Shows Attached Flash PROM . . . . . . . . . 137

Figure 4-28: SPI PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 4-29: Waveforms for Serial Peripheral Interface (SPI) Configuration . . . . . . . . 139

Figure 4-30: Multi-Package Layout for the M25Pxx Family on Spartan-3E Starter Kit 142

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Chapter 5: Master BPI Mode

Figure 5-1: Spartan-3E FPGA Configured from Parallel NOR Flash . . . . . . . . . . . . . . . . 144

Figure 5-2: Extended Spartan-3A Family FPGA Configured from

Parallel NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 5-3: FPGA Supports x8 Interface before Configuration and Optional

x16 Interface after Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 5-4: Parallel Daisy Chain using BPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 5-5: Serial Daisy Chains are Only Available for

Extended Spartan-3A Family BPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 5-6: Master BPI Mode Using Xilinx

Parallel Platform Flash PROMs (XCFxxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 5-7: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . . 161

Figure 5-8: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 5-9: Set Options for a Generic Parallel PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 5-10: Select Parallel PROM Size and Configuration Style . . . . . . . . . . . . . . . . . . 164

Figure 5-11: Select FPGA Bitstream Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 5-12: Generate Parallel PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 5-13: Parallel NOR Flash PROM/FPGA Power-On Timing if 3.3V Supply

is Last in Power-On Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 5-14: BPI Configuration Timing Waveform

(Spartan-3E BPI Down mode shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Chapter 6: Master Parallel Mode

Chapter 7: Slave Parallel (SelectMAP) Mode

Figure 7-1: Slave Parallel Mode

(Spartan-3E and Extended Spartan-3A Family FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 7-2: Slave Parallel Mode (Spartan-3 FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 7-3: Slave Parallel Daisy Chain for

Spartan-3E/Extended Spartan-3A Family FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 7-4: Slave Parallel Daisy Chain Using Any Modern Xilinx FPGA . . . . . . . . . . . 182

Figure 7-5: SelectMAP Continuous Data Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 7-6: SelectMAP Non-Continuous Data Loading with Controlled CSI_B. . . . . . 185

Figure 7-7: Non-Continuous SelectMAP Data Loading with Controlled CCLK. . . . . . 186

Figure 7-8: Configuration Abort Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 7-9: Readback Abort Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 7-10: Byte Swapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Chapter 8: Slave Serial Mode

Figure 8-1: Slave Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 9: JTAG Configuration Mode and Boundary-Scan

Figure 9-1: JTAG Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 9-2: Typical JTAG (IEEE 1149.1) Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

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Figure 9-3: Test Access Port (TAP) State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 9-4: Boundary-Scan Logic per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 9-5: Spartan-3 Generation Boundary-Scan Timing Waveforms . . . . . . . . . . . . . . 207

Figure 9-6: Target Interface Connector Dimensions and Pin Assignments . . . . . . . . . . 208

Figure 9-7: Double-click Configure Device (iMPACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 9-8: Configure Devices Using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 9-9: iMPACT Automatically Detects Devices on the JTAG Chain . . . . . . . . . . . 210

Figure 9-10: iMPACT Prompts for FPGA Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 9-11: iMPACT Automatically Adjusts FPGA Startup Clock

for JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 9-12: Click Bypass to Skip Platform Flash Programming . . . . . . . . . . . . . . . . . . . 211

Figure 9-13: Click Bypass to Skip CPLD Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 9-14: Double-Click Program to Configure FPGA via JTAG . . . . . . . . . . . . . . . . . 212

Figure 9-15: FPGA Programming Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Chapter 10: Internal Master SPI Mode

Figure 10-1: Spartan-3AN FPGA using Internal Master SPI Flash Mode . . . . . . . . . . . . 215

Figure 10-2: Spartan-3AN SPI_ACCESS Design Primitive . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 10-3: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . 220

Figure 10-4: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 10-5: Set Options for Spartan-3AN In-System Flash PROM. . . . . . . . . . . . . . . . . 222

Figure 10-6: Select a Spartan-3AN FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 10-7: Specify the FPGA Configuration Bitstream(s) . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 10-8: Review Spartan-3AN In-System Memory Formatting Settings . . . . . . . . . 225

Figure 10-9: Add FPGA Configuration Bitstream File(s) . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 10-10: iMPACT View of the Spartan-3AN In-System Flash Memory. . . . . . . . . 226

Figure 10-11: Generate the Spartan-3AN In-System Flash File. . . . . . . . . . . . . . . . . . . . . 226

Chapter 11: Configuration Bitstream Generator (BitGen) Settings

Chapter 12: Sequence of Events

Figure 12-1: Spartan-3 Generation FPGA Configuration Process. . . . . . . . . . . . . . . . . . . 239

Figure 12-2: FPGA Wake from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 12-3: Extended Spartan-3A Family and Spartan-3E Reset Circuitry

(Spartan-3 is similar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 12-4: FPGA Power-Up Timing Waveforms (Master Modes). . . . . . . . . . . . . . . . . 242

Figure 12-5: Clear Configuration Memory (Initialization). . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 12-6: Sample Control Pins (Mode Select, Variant Select) . . . . . . . . . . . . . . . . . . . 243

Figure 12-7: Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 12-8: Check Array ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 12-9: Load Configuration Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 12-10: Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 12-11: Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

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Figure 12-12: Default Start-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 12-13: Extended Spartan-3A Family, Spartan-3E FPGA

Configuration Logic Conceptual Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Chapter 13: Configuration-Related Design Primitives

Figure 13-1: BSCAN Primitive for Extended Spartan-3A Family FPGAs . . . . . . . . . . . . 253

Figure 13-2: STARTUP Primitive for

Extended Spartan-3A Family and Spartan-3E FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 13-3: CAPTURE Primitive for Extended Spartan-3A Family FPGAs

(other families are similar). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 13-4: ICAP Primitive (only available on

Extended Spartan-3A Family FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 13-5: DNA_PORT Primitive

(only available on Extended Spartan-3A Family FPGAs) . . . . . . . . . . . . . . . . . . . . . . . 259

Chapter 14: Reconfiguration and MultiBoot

Figure 14-1: Example Spartan-3E MultiBoot Application

using 1Mbyte Parallel Flash PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 14-2: Prepare a MultiBoot PROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 14-3: Select a PROM Supporting MultiBoot for Spartan-3E FPGAs . . . . . . . . . . 265

Figure 14-4: Select the Configuration Direction of the First MultiBoot Image . . . . . . . 266

Figure 14-5: Select a PROM Size and Add It to the Design . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 14-6: Confirm the PROM Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 14-7: Select the First MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . . . 267

Figure 14-8: Select the Second MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . 268

Figure 14-9: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . . 269

Figure 14-10: PROMGen Report File (*.prm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 14-11: Spartan-3A MultiBoot Example using XC3S700A and SPI Flash . . . . . . 279

Figure 14-12: Prepare a MultiBoot PROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 14-13: Select a PROM Supporting MultiBoot for

Extended Spartan-3A Family FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 14-14: SPI or Parallel Flash PROMs are Supported . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 14-15: Enter a PROM Density and Specify MultiBoot Image Start Locations. . 281

Figure 14-16: Confirm PROM Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Figure 14-17: Select the First (Default) Configuration Image . . . . . . . . . . . . . . . . . . . . . . 283

Figure 14-18: Select the Third MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . 283

Figure 14-19: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . 284

Figure 14-20: Extended Spartan-3A Family MultiBoot Configuration Mode Control . 286

Chapter 15: Protecting FPGA Designs

Figure 15-1: Setting Bitstream Generator Options from ISE Project Navigator . . . . . . 291

Figure 15-2: Bitstream Generator Security Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 15-3: Extended Spartan-3A Family DNA_PORT Design Primitive. . . . . . . . . . . 294

Figure 15-4: DNA_PORT Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

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Figure 15-5: Possible Options for DIN Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 15-6: Extended Spartan-3A Family FPGA Configures Normally . . . . . . . . . . . . . 298

Figure 15-7: Extended Spartan-3A Family FPGA Authenticates the

PROM Image Against Device DNA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 15-8: Authentication Fails Using an Unauthorized Copy . . . . . . . . . . . . . . . . . . . 299

Figure 15-9: Spartan-3E FPGA Authentication Example using

Commodity Flash PROM with Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 15-10: Spartan-3E FPGA Authenticates the PROM Image Against the

PROM’s Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 15-11: Intelligent Host Downloads a Spartan-3A Bitstream . . . . . . . . . . . . . . . . . 302

Figure 15-12: Host Reads Device DNA, Generates Authentication Value . . . . . . . . . . . 302

Figure 15-13: Host Writes Authentication Value to Enable FPGA Application . . . . . . 302

Figure 15-14: FPGA Authentication Using SHA-1 Secure EEPROM . . . . . . . . . . . . . . . . 303

Figure 15-15: Extended Spartan-3A Family Device DNA

Used as a Key to Protect Embedded Processing Applications . . . . . . . . . . . . . . . . . . . 306

Chapter 16: Configuration CRC

Figure 16-1: Conceptual Overview of Post-Configuration CRC Calculator . . . . . . . . . . 311

Figure 16-2: UCF Constraints for Post-Configuration CRC . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 16-3: Checking Block RAM Contents Using Simple Parity . . . . . . . . . . . . . . . . . 315

Chapter 17: Configuration Details

Chapter 18: Readback

Figure 18-1: Changing the SelectMAP Port from Write to Read Control . . . . . . . . . . . . 332

Figure 18-2: SelectMAP Status Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 18-3: IEEE 1532 JTAG Readback Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 18-4: Readback Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 18-5: Comparing Readback Data Using the .msd and .rbd Files . . . . . . . . . . . . . 344

Figure 18-6: Comparing Readback Data Using the .msk and .bit Files . . . . . . . . . . . . . . 345

Figure 18-7: Extended Spartan-3A Library Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Figure 18-8: Logic Allocation File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

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