PW4554
3
PIN ASSIGNMENT/DESCRIPTION
Pin No Pin Name
Functions
1 VIN
Power Input. A 1μF or larger value X5R ceramic capacitor is recommended to be placed as close as
possible to the input pin for decoupling purpose. Additional capacitance may be required to provide
a stable input voltage
2
P
_
P
_
R
_
Open-drain Power Presence Indication. The open-drain MOSFET turns on when the input voltage
is above the POR threshold but below the OVP threshold, and turns off otherwise. This pin is
capable of sinking 15mA (MIN) current to drive an LED. The maximum voltage rating for this pin is
5.5V. This pin is independent on the EN pin input
3
C
_
H
_
G
_
Open-drain Charge Indication. This pin outputs a logic low when a charge cycle starts and turns to
high impedance when the full-of-charge (FOC) condition is qualified. This pin is able to sink 15Ma
(MIN) current to drive an LED. When the charger is disabled, the CHG pin outputs high impedance.
4
E
_
N
_
Enable Input. This is a logic input pin to disable or enable the charger. Drive high to disable the
charger. When this pin is driven to low or left floating, the charger is enabled. This pin has an
internal 200kΩ pull-down resistor.
5 GND System Ground.
6
IMIN
Full-of-Charge (FOC) Current Programming Pin. Connect a resistor between this pin and the GND
pin to set the FOC current. The FOC current IMIN can be programmed by the following equation:
+
(
)
=
where RIMIN is in kΩ. The programmable range covers from 5mA to 120mA. FOC current will be
influenced by battery internal impedance and results in a small drift. When programmed to less
than 5mA, the stability is not guaranteed.
7
IREF
Charge-Current Programming and Monitoring Pin. Connect a resistor between this pin and the
GND pin to set the charge current limit determined by the following equation
:
(
)
=
where RIREF is in kΩ. The resistor should be placed very close to this pin. The IREF pin voltage also
monitors the actual charge current during the entire charge cycle, including the trickle,
constant-current, and constant-voltage phases. When disabled, VIREF = 0V.
8
BAT
Charger Output Pin. Connect this pin to the battery. A 1μF or larger X5R ceramic capacitor is
recommended for decoupling and stability purposes. When the EN pin is pulled to logic high, the
BAT output is disabled.
9 GND
(Expose Pad)
Thermal pad electrically connected to GND pin internally. This pad must be soldered to a large
PCB and connected to GND for maximum thermal dissipation.
GND
IMIN
IREF
BAT
H
_
_
_
GND
DFN-2x2-8L
( TOP VIEW )
VIN
PPR
CHG
EN
1
8
PW4554_2.0
Wuxi PWChip Semi Technology CO., LTD
www.pwchip.com