TI TMS470MF04207：高性能汽车级微控制器，带安全特性和CAN控制器

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TI-TMS470MF04207是一款高性能、汽车级的16/32位RISC闪存微控制器，它集成了多种关键特性，适用于严苛的汽车电子应用环境。该设备的主要特点包括： 1. 安全特性：TMS470MF04207具有高级安全功能，确保系统在运行过程中免受潜在威胁，如内置错误检测和纠正代码（ECC）用于闪存和SRAM数据保护。 2. 高性能：基于ARM Cortex-M33架构，这款微控制器提供了高效能，支持1.2 DMIPS/MHz的运算能力，适合需要高速处理的汽车应用。 3. 外部时钟支持：配备了两个外部时钟分频器（ECP），包括一个可编程低频外部时钟（ECLK）和一个专用的ECLK/HET引脚，适应不同的系统需求。 4. 通信接口：设备内置多个通信接口，如CAN控制器，支持高效的通信连接，同时具备Thumb2指令集，优化了程序执行效率。 5. 邮箱系统：拥有32个邮箱和16个额外邮箱，提供优化的邮件处理能力和奇偶校验功能，确保数据传输的准确性。 6. 内存保护与调试：通过内存保护单元（MPU）和调试模块，实现内存区域的隔离和故障诊断，方便软件开发和维护。 7. 外设接口：支持多缓存串行外设接口（MibSPI）和第三方支持的开放式架构，便于扩展和定制外设连接。 8. 芯片选通：提供12个芯片选通选择，便于系统集成和管理。 9. 缓冲器特性：配置了64个缓冲器，每个都包含奇偶校验，增强了数据存储的可靠性和稳定性。 10. 串行通信：包括两个通用异步收发器（UART/SCI）接口，最高可达80MHz系统时钟，满足高速数据传输需求。 11. 本地互连与网络支持：设计考虑到了本地网络连接的需求，具备相应的硬件支持。 TMS470MF04207是一款综合了高性能、安全性和多功能的微控制器，尤其适合汽车行业的严苛环境和复杂系统集成，是汽车电子设计中的理想选择。

TMS470MF04207

TMS470MF03107

ZHCS061C –JANUARY 2012

www.ti.com

Table 2-5. Peripheral Memory Chip Select Assignment (continued)

ADDRESS RANGE

PERIPHERAL

CONNECTING MODULE

SELECTS

BASE ADDRESS ENDING ADDRESS

ADC RAM 0xFF3E 0000 0xFF3F FFFF PCS[31]

HET RAM 0xFF46 0000 0xFF47 FFFF PCS[35]

NOTE

All used peripheral memory chip selects should decode down to the smallest possible

address for this particular peripheral configuration, starting from 4kB upwards. Unused

addresses should generate an illegal address error when accessed.

Table 2-6. System Peripheral Registers

ADDRESS RANGE

FRAME NAME

FRAME START ADDRESS FRAME ENDING ADDRESS

PSA 0xFE00 0000 0xFEFF FFFF

Flash Wrapper Registers 0xFFF8 7000 0xFFF8 7FFF

PCR Register 0xFFFF E000 0xFFFF E0FF

System Frame 2 Registers 0xFFFF E100 0xFFFF E1FF

CPU STC (LBIST) 0xFFFF E400 0xFFFF E4FF

ESM Register 0xFFFF F500 0xFFFF F5FF

RAM ECC Register 0xFFFF F900 0xFFFF F9FF

RTI Register 0xFFFF FC00 0xFFFF FCFF

VIM Register 0xFFFF FE00 0xFFFF FEFF

System Registers 0xFFFF FF00 0xFFFF FFFF

Table 2-7. Peripheral Select Map with Address Range

PERIPHERAL

CONNECTING MODULE BASE ADDRESS END ADDRESS

SELECTS

MibSPI2 0xFFF7 F600 0xFFF7 F7FF

PS[2]

MibSPI1 0xFFF7 F400 0xFFF7 F5FF

LIN/SCI1 0xFFF7 E500 0xFFF7 E5FF

PS[6]

LIN/SCI2 0xFFF7 E400 0xFFF7 E4FF

DCAN2 0xFFF7 DE00 0xFFF7 DFFF

PS[8]

DCAN1 0xFFF7 DC00 0xFFF7 DDFF

ADC 0xFFF7 C000 0xFFF7 C1FF PS[15]

GIO 0xFFF7 BC00 0xFFF7 BCFF PS[16]

HET 0xFFF7 B800 0xFFF7 B8FF PS[17]

2.1.3 Flash Memory

When in pipeline mode, the Flash operates with a system clock frequency of up to 80 MHz (versus a

system clock in non-pipeline mode of up to 28 MHz). Flash in pipeline mode is capable of accessing 128-

bit words and provides four 32-bit pipelined words to the CPU.

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Product Folder Links: TMS470MF04207 TMS470MF03107

TMS470MF04207

TMS470MF03107

www.ti.com

ZHCS061C –JANUARY 2012

NOTE

1. After a system reset, pipeline mode is disabled [FRDCNTL[2:0] is 000b, see the Flash

chapter in the TMS470M Series Technical Reference Manual (literature number

SPNU495)]. In other words, the device powers up and comes out of reset in non-

pipeline mode.

2. The flash external pump voltage (V

CCP

) is required for all operations (program,

erase, and read).

2.1.4 Flash Program and Erase

The TMS470MF04207/TMS470MF03107 devices flash contain one 384/256K-byte memory array (or

bank) and one 64K-byte bank for a total of up to 12 sectors. Table 2-8 and Table 2-9 show the

TMS470MF04207 and TMS470MF03107 flash memory banks and sectors.

The minimum size for an erase operation is one sector. The maximum size for a program operation is one

32-bit word.

Table 2-8. TMS470MF04207 Flash Memory Banks and Sectors

SECTOR MEMORY ARRAYS (OR

SEGMENT LOW ADDRESS HIGH ADDRESS

NO. BANKS)

0 16k 0x0000 0000 0x0000 3FFF

1 16k 0x0000 4000 0x0000 7FFF

2 32k 0x0000 8000 0x0000 FFFF

3 64k 0x0001 0000 0x0001 FFFF

BANK 0

(384K Bytes)

4 64k 0x0002 0000 0x0002 FFFF

5 64k 0x0003 0000 0x0003 FFFF

6 64k 0x0004 0000 0x0004 FFFF

7 64k 0x0005 0000 0x0005 FFFF

0 16k 0x0008 0000 0x0008 3FFF

1 16k 0x0008 4000 0x0008 7FFF

BANK 1

(1)

(64K Bytes)

2 16k 0x0008 8000 0x0008 BFFF

3 16k 0x0008 C000 0x0008 FFFF

(1) Bank 1 can be used as either EEPROM emulation space or as program space.

Table 2-9. TMS470MF03107 Flash Memory Banks and Sectors

SECTOR MEMORY ARRAYS (OR

SEGMENT LOW ADDRESS HIGH ADDRESS

NO. BANKS)

0 16k 0x0000 0000 0x0000 3FFF

1 16k 0x0000 4000 0x0000 7FFF

2 32k 0x0000 8000 0x0000 FFFF

BANK 0

(256K Bytes)

3 64k 0x0001 0000 0x0001 FFFF

4 64k 0x0002 0000 0x0002 FFFF

5 64k 0x0003 0000 0x0003 FFFF

0 16k 0x0008 0000 0x0008 3FFF

1 16k 0x0008 4000 0x0008 7FFF

BANK 1

(1)

(64K Bytes)

2 16k 0x0008 8000 0x0008 BFFF

3 16k 0x0008 C000 0x0008 FFFF

(1) Bank 1 can be used as either EEPROM emulation space or as program space.

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Product Folder Links: TMS470MF04207 TMS470MF03107

TMS470MF04207

TMS470MF03107

ZHCS061C –JANUARY 2012

www.ti.com

2.2 Terminal Functions

The terminal functions table (Table 2-10) identifies the pin names, the associated pin numbers, input

voltage, output voltage, whether the pin has any internal pullup/pulldown resistors and a functional pin

description. The TMS470MF04207 and TMS470MF03107 devices have the same pin out.

Table 2-10. Terminal Functions

TERMINAL INPUT

OUTPUT

VOLTAGE

(1)

IPU/IPD

(4)

DESCRIPTION

CURRENT

(3)

NAME 100 PIN

(2)

HIGH-END TIMER (HET)

HET[0] 39

Timer input capture or output compare. The

HET[1] 40

HET[15:0] applicable pins can be programmed as

HET[2] 49

general-purpose input/output (GIO) pins.

HET[3] 50

The high-resolution (HR) SHARE feature allows

even HR pins to share the next higher odd HR pin

HET[4] 53

structure. The next higher odd HR pin structure is

HET[5] 54

always implemented, even if the next higher odd

HET[6] 55

HR pad and/or pin itself is not.

Adaptive

HET[7] 56

Programmable Note: HET[15] is muxed with ECLK2 output. If

3.3-V I/O impedance 4

IPD (100 µA) ECLK2 output is enabled (through SYSPC1 register

HET[8] 57

at 0xFFFFFF00), ECLK2 is output on this pin and

HET[9] 58

HET[15] becomes an internal only HET channel.

HET[10] 59

Note: ECLK2 source select must be programmed

HET[11] 60

the same as ECLK1 due to device specific

implementation details.

HET[12] 61

Note: ECLK2 is enabled and ECLK2 divider is

HET[13] 62

programmed through ECP control register 1 in

HET[14] 63

System Frame 2 Registers (0xFFFFE128).

HET[15]/ECLK2 64

CAN CONTROLLER 1 (DCAN1)

CAN1STX 7 Adaptive DCAN1 transmit pin or GIO pin.

Programmable

3.3-V I/O impedance 4

CAN1SRX 8 DCAN1 receive pin or GIO pin.

IPU (100 µA)

CAN CONTROLLER 2 (DCAN2)

CAN2STX 37 Adaptive DCAN2 transmit pin or GIO pin

Programmable

3.3-V I/O impedance 4

CAN2SRX 38 DCAN2 receive pin or GIO pin

IPU (100 µA)

GENERAL-PURPOSE I/O (GIO)

GIOA[4]/INT[4] 5 General-purpose input/output pins.

Adaptive

GIOA[5]/INT[5] 6

They are interrupt-capable pins.

Programmable

3.3-V I/O impedance 4

IPD (100 µA)

GIOA[6]/INT[6] 15

GIOA[7]/INT[7] 16

(1) PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2) All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.

(3) The TMS470M device utilizes adaptive impedance 4 mA buffers that default to an adaptive impedance mode of operation. As a fail-safe,

the adaptive impedance features of the buffer may be disabled and revert the buffer to a standard buffer mode.

(4) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are inactive on input pins when PORRST is asserted)

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