7系列FPGA SelectIO资源用户指南（UG471 v1.10）

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本资源是Xilinx针对7系列FPGA（Field-Programmable Gate Array）产品的SelectIO资源用户指南，文档编号为UG471（v1.10），发布日期为2018年5月8日。SelectIO是一种高级I/O功能，专为优化高性能系统中的数据传输和选择功能而设计。该用户手册详细介绍了如何利用7Series FPGA中的SelectIO特性来提高系统的性能和灵活性。 SelectIO的主要目标是简化I/O配置，允许开发人员在硬件级别实现细粒度的数据路径选择和管理。它提供了多种功能，如数据包路由、数据宽度调整、并行总线管理以及低延迟的信号选择。通过这些功能，用户可以定制数据流处理，减少硬件资源消耗，并且支持不同的工作模式，如单选或多选。在使用SelectIO时，用户需要注意以下几点： 1. **无保证使用**：Xilinx提供的所有信息（Materials）是"按现状"提供，没有任何明示或暗示的保证，包括但不限于商品质量、不侵权或特定用途适用性。这意味着用户需要自行承担风险，Xilinx不对任何直接、间接损失或损害负责，即使这些损失是可以预见的，或者Xilinx本应预见。 2. **法律责任限制**：Xilinx不对Materials（包括用户对它们的使用）导致的任何损失或损害承担责任，不论是在合同、侵权（包括过失）、或其他法律理论下，即使这些损失或损害是可预见的，或是由于第三方行为引起的。 3. **适配性和兼容性**：在使用SelectIO之前，用户需要确保所选的FPGA型号与指南中的描述相符，并可能需要进行适配性测试，以确保其与系统其他组件的兼容性。 4. **安全性和合规性**：用户在设计和实施基于SelectIO的功能时，必须遵循所有适用的安全标准和法规，以确保系统的可靠性和符合性。 5. **学习和实施**：本指南包含详尽的步骤和示例，帮助用户理解和实施SelectIO技术，包括配置指南、代码示例以及故障排查技巧。 UG471 (v1.10) 是一个关键资源，为7 Series FPGA的开发人员提供了强大的工具，用于优化I/O性能，但同时也强调了使用过程中需要理解和遵守的免责声明和责任。对于想要利用SelectIO提升系统性能的工程师来说，这是不可或缺的技术参考文档。

16 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide

UG471 (v1.10) May 8, 2018

Chapter 1: SelectIO Resources

X-Ref Target - Figure 1-2

Figure 1-2: Regular HP IOB Diagram

X-Ref Target - Figure 1-3

Figure 1-3: Single-Ended (Only) HR IOB Diagram

X-Ref Target - Figure 1-4

Figure 1-4: Regular HR IOB Diagram

UG471_c1_04_010711

PA D

DIFFO_OUT

O_OUT

PADOUT

DCITERMDISABLE

DIFFI_IN

IBUFDISABLE

UG471_c1_05 _011010

PA D

PADOUT

DIFFI_IN

IBUFDISABLE

UG471_c1_06_011110

PA D

DIFFO_OUT

O_OUT

PADOUT

DIFFI_IN

IBUFDISABLE

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18 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide

UG471 (v1.10) May 8, 2018

Chapter 1: SelectIO Resources

Supply Voltages for the SelectIO Pins

CCO

The V

CCO

supply is the primary power supply of the 7 series I/O circuitry. The V

CCO (V)

columns in Table 1-55 provide the V

CCO

requirements for each of the supported I/O

standards, and illustrate the V

CCO

requirements for both inputs and outputs as well as the

optional internal differential termination circuit. All V

CCO

pins for a given I/O bank must

be connected to the same external voltage supply on the board, and as a result all of the

I/O within a given I/O bank must share the same V

CCO

level. The V

CCO

voltage must

match the requirements for the I/O standards that have been assigned to the I/O bank. An

incorrect V

CCO

voltage can result in loss of functionality or damage to the device. The

7 series power supply requirements, including power-on and power-off sequencing, are

described in the 7 series FPGA data sheets.

In HP I/O banks, if the I/O standard voltage requirement is <

1.8V, but a V

CCO

> 2.5V is

applied, the device automatically enters an overvoltage protection mode. Reconfiguring

the device with the correct V

CCO

level restores normal operation.

REF

Single-ended I/O standards with a differential input buffer require an input reference

voltage (V

REF

). When V

REF

is required within an I/O bank, the two multi-function V

REF

pins for the bank must be used as V

REF

supply inputs. 7 series FPGAs can optionally use an

internally generated reference voltage by enabling the INTERNAL_VREF constraint. For

more information on this constraint, see 7 Series FPGA SelectIO Attributes/Constraints,

page 46.

CCAUX

The global auxiliary (V

CCAUX

) supply rail is primarily used for providing power to the

various block feature’s interconnect logic inside the 7 series FPGAs. In the I/O banks,

CCAUX

is also used to power input buffer circuits for some of the I/O standards. These

include all of the single-ended I/O standards at or below 1.8V, and also some of the 2.5V

standards (HR I/O banks only). Additionally, the V

CCAUX

rail provides power to the

bank’s differential input buffer circuits used for the differential and V

REF

I/O standards.

The 7 series power supply requirements, including power-on and power-off sequencing,

are described in the 7 series FPGA data sheets.

CCAUX_IO

The auxiliary I/O (V

CCAUX_IO

) supply rail is only present in HP I/O banks and provides

power to the I/O circuitry. The Kintex-7 and Virtex-7 FPGAs data sheets contain a table

titled Maximum Physical Interface (PHY) Rate for Memory Interfaces that references

CCAUX_IO

. This table indicates how the V

CCAUX_IO

pins can be powered at either 1.8V

(default), or optionally at 2.0V to achieve higher frequency performance for certain types

of memory interfaces. Although this table is designed for memory interfaces, it can also

provide guidance on powering V

CCAUX_IO

for other high-speed single-ended interfaces

based on the target bit rates. The table does not apply to LVDS, which uses a different type

of driver circuit than the single-ended drivers that are more affected by the V

CCAUX_IO

level. Thus, for LVDS interfaces, it does not matter which voltage level the V

CCAUX_IO

rail

is powered at. The default value of 1.8V affords a lower-power consumption and provides

very close to the same performance in the I/Os. The 2.0V option is available when the

slightly-increased performance is required for the very fastest bit rates supported for the

single-ended drivers.

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7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 19

UG471 (v1.10) May 8, 2018

7 Series FPGA DCI—Only available in the HP I/O banks

There is a design constraint for I/O nets and primitives called VCCAUX_IO, which should

be specified in the design if the V

CCAUX_IO

pins for any banks are to be set at 2.0V. See

7 Series FPGA SelectIO Attributes/Constraints, page 46 for information on this constraint.

The V

CCAUX_IO

pins are connected together internally inside Kintex-7 and Virtex-7 device

packages in groups of three or four HP I/O banks. The package files chapter of

UG475

: 7 Series FPGA Packaging and Pinout Specification contains links to the ASCII package

files, and the figures in the device diagrams chapter indicate which device/package

combinations contain HP I/O banks with V

CCAUX_IO

pins. The ASCII package files

indicate which bank’s V

CCAUX_IO

pins are grouped together inside the package. The

CCAUX_IO

package pin names have the syntax VCCAUX_IO_G#, where the # is the

internal group number. The package files contain a column called “VCCAUX Group” that

shows for every I/O pin which V

CCAUX

group that I/O bank is associated with. All I/O

pins that are in the same V

CCAUX_IO

group must have VCCAUX_IO constraints on their

nets or primitives that are compatible. All V

CCAUX_IO

pins that are grouped together

should be tied to the same voltage rail on the board. FBG packages for Kintex-7 devices

contain V

CCAUX_IO

pins but are no connects internally. All HP I/O banks in those packages

are powered from the main V

CCAUX

rail instead.

State of I/Os During and After Configuration

7 series FPGAs have pins dedicated to configuration functions contained in I/O bank 0.

Banks 14 and 15 also contain I/O pins known as multi-function or multi-purpose pins that

can also be used for configuration, but then convert to normal I/O pins after configuration

is complete. Additionally in SSI devices, pins in banks 11, 12, 17, 18, 20, and 21 have

restrictions during configuration similar to multi-function pins. However, pins in these

banks do not have any configuration functions.

In devices where bank 14 and/or bank 15 are HR banks and configured with a V

CCO

requirement <

1.8V, inputs might have a 0-1-0 transition to the interconnect logic during

configuration if the input is tied to 0 or floating and the configuration voltage is >

2.5V. For

further details, refer to UG470

: 7 Series FPGAs Configuration User Guide.

7 Series FPGA DCI—Only available in the HP I/O banks

Introduction

As FPGAs get bigger and system clock speeds get faster, PC board design and

manufacturing becomes more difficult. With ever faster edge rates, maintaining signal

integrity becomes a critical issue. PC board traces must be properly terminated to avoid

reflections or ringing.

To terminate a trace, resistors are traditionally added to make the output and/or input

match the impedance of the receiver or driver to the impedance of the trace. However, due

to increased device I/Os, adding resistors close to the device pins increases the board area

and component count, and can in some cases be physically impossible. To address these

issues and to achieve better signal integrity, Xilinx developed the digitally controlled

impedance (DCI) technology.

Depending on the I/O standard, DCI can either control the output impedance of a driver,

or add a parallel termination present at the driver and/or receiver, with the goal of

accurately matching the characteristic impedance of the transmission line. DCI actively

adjusts these impedances inside the I/O to calibrate to external precision reference

resistors placed on the VRN and VRP pins. This compensates for changes in I/O

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20 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide

UG471 (v1.10) May 8, 2018

Chapter 1: SelectIO Resources

impedance due to process variation. It also continuously adjusts the impedances to

compensate for variations of temperature and supply voltage fluctuations.

For the I/O standards with controlled impedance drivers, DCI controls the driver

impedance to either match the two reference resistors, or for some standards, to match half

the value of these reference resistors.

For the I/O standards with controlled parallel termination, DCI provides the parallel

termination for both transmitters and receivers. This eliminates the need for termination

resistors on the board, reduces board routing difficulties and component count, and

improves signal integrity by eliminating stub reflection. Stub reflection occurs when

termination resistors are located too far from the end of the transmission line. With DCI,

the termination resistors are as close as possible to the output driver or the input buffer,

thus, eliminating stub reflections. DCI is only available in 7 series FPGAs HP I/O banks.

DCI is not available in HR I/O banks.

Xilinx DCI

DCI uses two multi-purpose reference pins in each I/O bank to control the impedance of

the driver or the parallel-termination value for all of the I/Os of that bank. The N reference

pin (VRN) must be pulled up to V

CCO

by a reference resistor, and the P reference pin (VRP)

must be pulled down to ground by another reference resistor. The value of each reference

resistor should be either equal to the characteristic impedance of the PC board traces or

twice that value.

To implement DCI in a design:

1. Assign one of the DCI I/O standards in an HP I/O bank (see Table 1-2 and Table 1-3).

2. Connect the VRN multi-function pin to a precision resistor tied to the V

CCO

rail for the

same bank.

3. Connect the VRP multi-function pin to a precision resistor tied to ground.

The following sections discuss how to determine the precision resistor values for VRN and

VRP for the different I/O standards. Only one set of VRN and VRP resistors is used for

each bank, so all DCI standards within each bank must be able to share the same external

resistance values. If several I/O banks in the same I/O bank column are using DCI, and all

of those I/O banks use the same VRN/VRP resistor values, the internal VRN and VRP

nodes can be cascaded so that only one pair of pins for all of the I/O banks in the entire I/

O column is required to be connected to precision resistors. This option is called DCI

cascading and is detailed in DCI Cascading, page 22. This section also describes how to

determine if I/O banks share the same I/O bank column. If DCI I/O standards are not

used in the bank, these pins are available as regular I/O pins. UG475

: 7 Series FPGAs

Packaging and Pinout Specifications gives detailed pin descriptions.

DCI adjusts the impedance of the I/O by selectively turning transistors in the I/Os on or

off. The impedance is adjusted to match the external reference resistors. The adjustment

starts during the device startup sequence. By default, the DONE pin does not go High until

the first part of the impedance adjustment process is completed.

The DCI calibration can be reset by instantiating the DCIRESET primitive. Toggling the

RST input to the DCIRESET primitive while the device is operating, resets the DCI state

machine and restarts the calibration process. All I/Os using DCI will be unavailable until

the LOCKED output from the DCIRESET block is asserted. This functionality is useful in

applications where the temperature and/or supply voltage changes significantly from

device power-up to the nominal operating condition.

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