IEEE 1149.7：减小引脚的增强型测试访问端口标准

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"这篇文档是关于JTAG协议的两个重要标准——IEEE 1149.1和1149.7的介绍。1149.7标准旨在减少专门用于测试和调试的芯片引脚数量，同时增强测试访问端口(TAP)的功能，作为1149.1标准的补充增强版。它提供了如热插拔免疫、电源管理、扫描吞吐量优化、仪器访问以及对定制技术的访问等特性，对调试工作带来了显著的改进。此外，它还增强了边界扫描架构，确保全面支持测试，特别适用于多核SoC或多芯片封装中的测试和调试接口。" IEEE 1149.1是测试访问端口（TAP）和边界扫描架构的原始标准，它在电子行业中广泛应用于集成电路的测试和调试。该标准定义了一组接口，允许外部设备通过TAP控制器访问内部电路，以便进行功能测试、故障定位和编程。边界扫描链是其核心部分，允许在不改变电路正常操作的情况下，检测和修改内部连接。而IEEE 1149.7标准则是对1149.1的扩展，它引入了几个关键的新特性： 1. **减少引脚数量**：1149.7通过更高效的数据传输机制，减少了专门用于测试的引脚，从而降低了芯片的封装成本。 2. **热插拔免疫**：这个特性允许设备在系统运行时插入或移除，而不影响系统的稳定性和安全性。 3. **电源管理**：通过优化电源管理，1149.7可以在不影响系统性能的情况下，有效地进行测试和调试。 4. **扫描吞吐量优化**：提高数据传输速度，加快测试过程，节省时间并提高生产效率。 5. **仪器访问**：允许访问更多的内部设备和功能，提供更广泛的调试可能性。 6. **对定制技术的访问**：为特定应用或技术提供了额外的访问途径，增强了灵活性。 1149.7标准特别适用于系统级封装(SIP)和多芯片封装(POP)，其中包含多个集成电路，需要高效且灵活的测试解决方案。在多核SoC中，每个核心可能需要独立的调试接口，1149.7提供了这样的能力，使得系统级的调试变得更加便捷。 JTAG协议的1149.1和1149.7标准是现代电子设计中不可或缺的工具，它们提升了测试和调试的效率，同时也适应了芯片集成度不断提高和系统复杂性增加的需求。对于硬件开发者和测试工程师来说，深入理解这些标准对于提高工作效率和产品质量至关重要。

Paper ET3.1 INTERNATIONAL TEST CONFERENCE 1

Doing More with Less – An IEEE 1149.7 Embedded Tutorial :

Standard for Reduced-pin and Enhanced-functionality Test Access Port and

Boundary-Scan Architecture

Adam W Ley

ASSET InterTech, Inc. Richardson TX, USA

Abstract

IEEE Std 1149.7 offers a means to reduce chip pins

dedicated to test (and debug) access while enhancing the

functionality of the Test Access Port (TAP) as a

complementary superset of the original IEEE Std 1149.1

(JTAG). Extended features such as hot-plug immunity,

power management, optimization of scan throughput,

access to instrumentation, and access to custom

technologies provide welcome improvements for debug.

Further, the boundary-scan architecture is bolstered to

ensure full support for test. This important advancement in

test and debug interfaces is well suited for access to

multiple cores on SOC or multiple die in SIP or POP.

1. Introduction

In the 1980s, the Joint Test Action Group (JTAG) was

formed to address a growing concern about diminishing

test access to chips on boards due to the adoption of

surface-mount assembly methods and ongoing

miniaturization of chip packages. In 1990, their efforts

culminated in the ratification of IEEE Std 1149.1 –

Standard Test Access Port and Boundary-Scan

Architecture. While 1149.1 was firmly rooted in the need

to solve the problems of board test, as exemplified by the

provision for boundary scan, the proponents of the

standard realized the need for a generalized means of low-

level access to components on boards and in systems that

would suit a wide range of uses. As a result, the 1149.1

test access port (TAP), as specified, has met this need.

In fact, even before the ink was dry, the 1149.1 TAP was

being exploited for purposes beyond board test. In these

early days, its utility was deployed to support access to

chips for in-circuit emulation (debug), albeit often with

additional pins for proprietary signals. Somewhat later, the

ubiquity of the 1149.1 TAP was exploited in a normative

sense for in-system configuration of programmable

devices by way of IEEE Std 1532. Later still, use of the

1149.1 TAP as a debug interface was standardized by

NEXUS 5001 (although still requiring additional signaling

for many cases). Today, for the same reasons of utility and

ubiquity, the 1149.1 TAP is considered the most likely

means of access to chips that support embedded

instruments per P1687 (informally known as Internal

JTAG or IJTAG).

Notwithstanding the exceptional merits of the 1149.1

TAP, ongoing industry momentum toward greater

miniaturization and still more integration led some to the

conclusion that a makeover was needed [1]. In particular,

they proposed to enhance its functionality and utility in

applications debug, but also to reduce pins to be better

suited to multi-core/ multi-die architectures. IEEE Std

1149.7 [2, 3, 4, 5] has been developed to meet these needs

[6, 7, 8, 9, 10, 11, 12].

1.1 What is IEEE 1149.7

IEEE 1149.7 is a standard for a test access port and

associated architecture that offers reduced pins and

enhanced functionality. With regard to pin reduction,

whereas the conventional 1149.1 TAP (TAP.1) requires at

least four signals (with a fifth, for test reset, being

optional), the reduced-pin 1149.7 TAP (TAP.7) requires

only two signals (with the possibility for encoding the

optional test reset function onto these). Further, with

regard to functionality enhancement, it is expected that, in

many cases, extended signaling needs for uses such as

applications debug can be met on no more than two pins.

Even while delivering these benefits, 1149.7 has taken

great pains to preserve the investment that the industry has

made in 1149.1 for chips and on boards. Particularly,

1149.7 adopts the entirety of the 1149.1 boundary-scan

architecture to fully support board test and in-system

configuration. Further, 1149.7 does not replace 1149.1, but

rather adapts it and extends it, building upon its foundation

and legacy. For example, as illustrated in Figure 1, an

1149.1 chip can be adapted easily to provide a TAP.7. As

well, TAP.7s can coexist with TAP.1s on boards and, in

some cases, even on the same board-level TAP

connections.

1149.1

1149.7 chip

1149.1

“core”

P1149.7

adapter

“before” “after”

1149.1

1149.7 chip

1149.1

“core”

1149.1

“core”

P1149.7

adapter

“before” “after”

Figure 1—Adaptation of 1149.1 to 1149.7

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