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首页联想V450 Y430电路图PDF文档
联想V450 Y430电路图PDF文档
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更新于2024-07-24
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"联想V450 Y430电路图PDF文档la-4141"
根据提供的信息,我们可以了解到这是一份与联想V450(可能还有Y430)笔记本电脑相关的电路图,具体是PDF文档形式,文档编号为LA-4141,修订版本为1.0。这份电路图属于Compal Electronics, Inc.的机密资料,包含了敏感的商业秘密和工程设计信息。Compal Electronics是一家知名的原始设计制造商(ODM),为多个品牌制造电子设备,包括笔记本电脑。
电路图是电子工程中的关键文档,它详尽地描绘了电子设备内部的电气连接和组件布局。在联想V450 Y430的电路图中,我们可能会找到以下关键信息:
1. **系统主板布局**:电路图会显示主板上的各个组件位置,包括CPU、内存插槽、硬盘接口、显卡、无线网卡、电池接口等。
2. **电源管理**:电路图将展示电源管理电路,包括AC适配器接口、电池充电电路和电源开关电路。
3. **I/O接口**:USB端口、HDMI、VGA、网络接口、音频输入输出等都会在图中有所体现,显示它们是如何连接到主板上的。
4. **显示系统**:对于Y430,可能会有集成显卡和独立显卡的连接路径,以及如何与液晶显示屏交互的详细信息。
5. **散热系统**:风扇和热管的连接,以及温度传感器的位置,有助于理解设备的冷却机制。
6. **内存和存储**:内存条和硬盘的连接方式,以及任何其他存储解决方案(如SSD)的接口。
7. **BIOS和控制系统**:电路图将揭示BIOS芯片和其他控制芯片的位置,这些芯片负责初始化系统并处理硬件设置。
8. **信号路径**:所有输入输出信号的路径,如键盘、触摸板、摄像头和各种传感器的信号如何传递到主板。
9. **安全特性**:可能包含防止未经授权访问或篡改的电子安全措施,例如防盗电路或硬件加密。
10. **故障排查**:对于维修人员来说,电路图是诊断和修复硬件问题的重要工具,它提供了每个组件如何相互作用的清晰视图。
不过,由于电路图被标记为Compal的机密数据,这意味着它不能被随意传播或使用,除非得到Compal Electronics的书面授权。这样的限制是为了保护公司的知识产权,防止技术泄露给竞争对手。
联想V450 Y430电路图是理解和维护这款笔记本电脑内部工作原理的关键文件,但同时也需尊重其保密性。对于专业维修人员和电子爱好者而言,这类图纸是宝贵的参考资料。
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D11
DDR_A_D43
DDR_A_D23
DDR_A_D5
DDR_A_D39
DDR_A_D9
DDR_A_D24
DDR_A_D8
DDR_A_D52
DDR_A_D38
DDR_A_D0
DDR_A_D13
DDR_A_D55
DDR_A_D16
DDR_A_D48
DDR_A_D40
DDR_A_D18
DDR_A_D51
DDR_A_D3
DDR_A_D44
DDR_A_D54
DDR_A_D58
DDR_A_D32
DDR_A_D53
DDR_A_D26
DDR_A_D2
DDR_A_D19
DDR_A_D42
DDR_A_D7
DDR_A_D29
DDR_A_D1
DDR_A_D37
DDR_A_D17
DDR_A_D12
DDR_A_D10
DDR_A_D6
DDR_A_D45
DDR_A_D50
DDR_A_D46
DDR_A_D61
DDR_A_D20
DDR_A_D47
DDR_A_D4
DDR_A_D41
DDR_A_D57
DDR_A_D27
DDR_A_D14
DDR_A_D36
DDR_A_D15
DDR_A_D30
DDR_A_D49
DDR_A_D63
DDR_A_D62
DDR_A_D60
DDR_A_D59
DDR_A_D35
DDR_A_D21
DDR_A_D31
DDR_A_D28
DDR_A_D56
DDR_A_D25
DDR_A_D34
DDR_A_D22
DDR_A_D33
DDR_B_D11
DDR_B_D46
DDR_B_D0
DDR_B_D7
DDR_B_D44
DDR_B_D57
DDR_B_D30
DDR_B_D35
DDR_B_D3
DDR_B_D27
DDR_B_D15
DDR_B_D40
DDR_B_D37
DDR_B_D19
DDR_B_D23
DDR_B_D49
DDR_B_D25
DDR_B_D47
DDR_B_D36
DDR_B_D8
DDR_B_D48
DDR_B_D18
DDR_B_D52
DDR_B_D2
DDR_B_D9
DDR_B_D60
DDR_B_D62
DDR_B_D50
DDR_B_D39
DDR_B_D56
DDR_B_D22
DDR_B_D28
DDR_B_D51
DDR_B_D45
DDR_B_D17
DDR_B_D6
DDR_B_D61
DDR_B_D58
DDR_B_D1
DDR_B_D54
DDR_B_D5
DDR_B_D31
DDR_B_D41
DDR_B_D12
DDR_B_D20
DDR_B_D14
DDR_B_D38
DDR_B_D16
DDR_B_D32
DDR_B_D33
DDR_B_D63
DDR_B_D42
DDR_B_D55
DDR_B_D59
DDR_B_D13
DDR_B_D26
DDR_B_D4
DDR_B_D53
DDR_B_D29
DDR_B_D43
DDR_B_D24
DDR_B_D21
DDR_B_D10
DDR_B_D34
DDR_A_DM7
DDR_A_DM5
DDR_A_DM2
DDR_A_DM1
DDR_A_DM6
DDR_A_DM4
DDR_A_DM0
DDR_A_DM3
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#3
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#4
DDR_A_DQS#7
DDR_A_DQS#6
DDR_B_MA14
DDR_B_MA9
DDR_B_MA7
DDR_B_MA0
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_B_MA5
DDR_B_MA11
DDR_B_MA3
DDR_B_MA8
DDR_B_MA10
DDR_B_MA6
DDR_B_MA12
DDR_B_MA1
DDR_B_DQS#1
DDR_B_DQS#5
DDR_B_DQS#7
DDR_B_DQS#0
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS6
DDR_B_DM3
DDR_B_DM0
DDR_B_DM1
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE# DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_A_DQS4
DDR_A_DQS3
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS5
DDR_A_DQS2
DDR_A_MA14
DDR_A_MA0
DDR_A_MA1
DDR_A_MA4
DDR_A_MA2
DDR_A_MA3
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_D[0..63]<14> DDR_B_D[0..63]<15>
DDR_A_DM[0..7] <14>
DDR_B_MA[0..14] <15>
DDR_B_DM[0..7] <15>
DDR_B_BS#0 <15>
DDR_B_BS#1 <15>
DDR_B_BS#2 <15>
DDR_A_BS#0 <14>
DDR_A_BS#1 <14>
DDR_A_BS#2 <14>
DDR_A_CAS# <14>
DDR_A_RAS# <14>
DDR_A_WE# <14>
DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_WE# <15>
DDR_A_DQS[0..7] <14>
DDR_A_DQS#[0..7] <14>
DDR_B_DQS[0..7] <15>
DDR_B_DQS#[0..7] <15>
DDR_A_MA[0..14] <14>
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Cantiga GMCH (2/6)-DDRII
B
952Friday, May 02, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Cantiga GMCH (2/6)-DDRII
B
952Friday, May 02, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Cantiga GMCH (2/6)-DDRII
B
952Friday, May 02, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
DDR SYSTEM MEMORY B
U26E
CANTIGA ES_FCBGA1329GM@
DDR SYSTEM MEMORY B
U26E
CANTIGA ES_FCBGA1329GM@
SB_DQ_0
AK47
SB_DQ_1
AH46
SB_DQ_2
AP47
SB_DQ_3
AP46
SB_DQ_4
AJ46
SB_DQ_5
AJ48
SB_DQ_6
AM48
SB_DQ_7
AP48
SB_DQ_8
AU47
SB_DQ_9
AU46
SB_DQ_10
BA48
SB_DQ_11
AY48
SB_DQ_12
AT47
SB_DQ_13
AR47
SB_DQ_14
BA47
SB_DQ_15
BC47
SB_DQ_16
BC46
SB_DQ_17
BC44
SB_DQ_18
BG43
SB_DQ_19
BF43
SB_DQ_20
BE45
SB_DQ_21
BC41
SB_DQ_22
BF40
SB_DQ_23
BF41
SB_DQ_24
BG38
SB_DQ_25
BF38
SB_DQ_26
BH35
SB_DQ_27
BG35
SB_DQ_28
BH40
SB_DQ_29
BG39
SB_DQ_30
BG34
SB_DQ_31
BH34
SB_DQ_32
BH14
SB_DQ_33
BG12
SB_DQ_34
BH11
SB_DQ_35
BG8
SB_DQ_36
BH12
SB_DQ_37
BF11
SB_DQ_38
BF8
SB_DQ_39
BG7
SB_DQ_40
BC5
SB_DQ_41
BC6
SB_DQ_42
AY3
SB_DQ_43
AY1
SB_DQ_44
BF6
SB_DQ_45
BF5
SB_DQ_46
BA1
SB_DQ_47
BD3
SB_DQ_48
AV2
SB_DQ_49
AU3
SB_DQ_50
AR3
SB_DQ_51
AN2
SB_DQ_52
AY2
SB_DQ_53
AV1
SB_DQ_54
AP3
SB_DQ_55
AR1
SB_DQ_56
AL1
SB_DQ_57
AL2
SB_DQ_58
AJ1
SB_DQ_59
AH1
SB_DQ_60
AM2
SB_DQ_61
AM3
SB_DQ_62
AH3
SB_DQ_63
AJ3
SB_BS_0
BC16
SB_BS_1
BB17
SB_BS_2
BB33
SB_RAS#
AU17
SB_CAS#
BG16
SB_WE#
BF14
SB_DM_0
AM47
SB_DM_1
AY47
SB_DM_2
BD40
SB_DM_3
BF35
SB_DM_4
BG11
SB_DM_5
BA3
SB_DM_6
AP1
SB_DM_7
AK2
SB_DQS_0
AL47
SB_DQS_1
AV48
SB_DQS_2
BG41
SB_DQS_3
BG37
SB_DQS_4
BH9
SB_DQS_5
BB2
SB_DQS_6
AU1
SB_DQS_7
AN6
SB_DQS#_0
AL46
SB_DQS#_1
AV47
SB_DQS#_2
BH41
SB_DQS#_3
BH37
SB_DQS#_4
BG9
SB_DQS#_5
BC2
SB_DQS#_6
AT2
SB_DQS#_7
AN5
SB_MA_0
AV17
SB_MA_1
BA25
SB_MA_2
BC25
SB_MA_3
AU25
SB_MA_4
AW25
SB_MA_5
BB28
SB_MA_6
AU28
SB_MA_7
AW28
SB_MA_8
AT33
SB_MA_9
BD33
SB_MA_10
BB16
SB_MA_11
AW33
SB_MA_12
AY33
SB_MA_13
BH15
SB_MA_14
AU33
DDR SYSTEM MEMORY A
U26D
CANTIGA ES_FCBGA1329GM@
DDR SYSTEM MEMORY A
U26D
CANTIGA ES_FCBGA1329GM@
SA_BS_0
BD21
SA_BS_1
BG18
SA_BS_2
AT25
SA_RAS#
BB20
SA_CAS#
BD20
SA_WE#
AY20
SA_DM_0
AM37
SA_DM_1
AT41
SA_DM_2
AY41
SA_DM_3
AU39
SA_DM_4
BB12
SA_DM_5
AY6
SA_DM_6
AT7
SA_DM_7
AJ5
SA_DQS_0
AJ44
SA_DQS_1
AT44
SA_DQS_2
BA43
SA_DQS_3
BC37
SA_DQS_4
AW12
SA_DQS_5
BC8
SA_DQS_6
AU8
SA_DQS_7
AM7
SA_DQS#_0
AJ43
SA_DQS#_1
AT43
SA_DQS#_2
BA44
SA_DQS#_3
BD37
SA_DQS#_4
AY12
SA_DQS#_5
BD8
SA_DQS#_6
AU9
SA_DQS#_7
AM8
SA_MA_0
BA21
SA_MA_1
BC24
SA_MA_2
BG24
SA_MA_3
BH24
SA_MA_4
BG25
SA_MA_5
BA24
SA_MA_6
BD24
SA_MA_7
BG27
SA_MA_8
BF25
SA_MA_9
AW24
SA_MA_10
BC21
SA_MA_11
BG26
SA_MA_12
BH26
SA_MA_13
BH17
SA_MA_14
AY25
SA_DQ_0
AJ38
SA_DQ_1
AJ41
SA_DQ_2
AN38
SA_DQ_3
AM38
SA_DQ_4
AJ36
SA_DQ_5
AJ40
SA_DQ_6
AM44
SA_DQ_7
AM42
SA_DQ_8
AN43
SA_DQ_9
AN44
SA_DQ_10
AU40
SA_DQ_11
AT38
SA_DQ_12
AN41
SA_DQ_13
AN39
SA_DQ_14
AU44
SA_DQ_15
AU42
SA_DQ_16
AV39
SA_DQ_17
AY44
SA_DQ_18
BA40
SA_DQ_19
BD43
SA_DQ_20
AV41
SA_DQ_21
AY43
SA_DQ_22
BB41
SA_DQ_23
BC40
SA_DQ_24
AY37
SA_DQ_25
BD38
SA_DQ_26
AV37
SA_DQ_27
AT36
SA_DQ_28
AY38
SA_DQ_29
BB38
SA_DQ_30
AV36
SA_DQ_31
AW36
SA_DQ_32
BD13
SA_DQ_33
AU11
SA_DQ_34
BC11
SA_DQ_35
BA12
SA_DQ_36
AU13
SA_DQ_37
AV13
SA_DQ_38
BD12
SA_DQ_39
BC12
SA_DQ_40
BB9
SA_DQ_41
BA9
SA_DQ_42
AU10
SA_DQ_43
AV9
SA_DQ_44
BA11
SA_DQ_45
BD9
SA_DQ_46
AY8
SA_DQ_47
BA6
SA_DQ_48
AV5
SA_DQ_49
AV7
SA_DQ_50
AT9
SA_DQ_51
AN8
SA_DQ_52
AU5
SA_DQ_53
AU6
SA_DQ_54
AT5
SA_DQ_55
AN10
SA_DQ_56
AM11
SA_DQ_57
AM5
SA_DQ_58
AJ9
SA_DQ_59
AJ8
SA_DQ_60
AN12
SA_DQ_61
AM13
SA_DQ_62
AJ11
SA_DQ_63
AJ12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GM_ENVDD
GMCH_ENBKL
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_R
PEGCOMP
GMCH_CRT_DATA
GMCH_CRT_CLK
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N0
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N13
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_N13
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_P14
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P12
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P1
PCIE_GTX_C_MRX_P3
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N1
TVC_DAC
TVB_DAC
TVA_DAC
TVB_DAC
TVA_DAC
TVC_DAC
LVDS_SDA
LVDS_SCL
LVDS_A0
LVDS_A1#
LVDS_B1#
LVDS_A2#
LVDS_B2#
LVDS_A1
LVDS_B0
LVDS_A2
LVDS_B2
LVDS_B0#
LVDS_B1
LVDS_A0#
LVDS_BCLK#
LVDS_BCLK
LVDS_ACLK#
LVDS_ACLK
GMCH_CRT_B<25>
GMCH_CRT_G<25>
GMCH_CRT_R<25>
GMCH_CRT_DATA<25>
PCIE_MTX_C_GRX_N[0..15] <16>
PCIE_GTX_C_MRX_P[0..15] <16>
PCIE_GTX_C_MRX_N[0..15] <16>
PCIE_MTX_C_GRX_P[0..15] <16>
GMCH_ENBKL<24>
GM_ENVDD<24>
GMCH_CRT_CLK<25>
TMDS_B_CLK <23>
TMDS_B_CLK# <23>
TMDS_B_DATA0 <23>
TMDS_B_DATA0# <23>
TMDS_B_DATA1 <23>
TMDS_B_DATA1# <23>
TMDS_B_DATA2 <23>
TMDS_B_DATA2# <23>
TMDS_B_HPD# <23>
LVDS_SDA<24>
LVDS_SCL<24>
LVDS_BCLK#
LVDS_BCLK
LVDS_ACLK#<24>
LVDS_ACLK<24>
LVDS_A1#<24>
LVDS_A2#<24>
LVDS_A0#<24>
LVDS_A1<24>
LVDS_A2<24>
LVDS_A0<24>
LVDS_B1#
LVDS_B2#
LVDS_B0#
LVDS_B1
LVDS_B2
LVDS_B0
GMCH_CRT_VSYNC<25>
GMCH_CRT_HSYNC<25>
+3VS
+VCC_PEG
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Cantiga GMCH (3/6)-VGA/LVDS/TV
Custom
10 52Friday, May 02, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Cantiga GMCH (3/6)-VGA/LVDS/TV
Custom
10 52Friday, May 02, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Cantiga GMCH (3/6)-VGA/LVDS/TV
Custom
10 52Friday, May 02, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
Please check Power
source if want
support IAMT
Layout Note: Place 150
Ohmtermination resistors
close to GMCH
Note: All LVDS data
signals/and it's compliments
should be routed
Differentially
For Calero: 1.5Kohm
For Crestline:2.4kohm
For Calero: 255ohm
For Crestline:1.3kohm
PEGCOMP trace width
and spacing is 20/25 mils.
Place the resistor within 500mils
(1.27mm)of the (G)MCH
For Cantiga:1.02kohm
For Cantiga:2.37kohm
20mil
000 = FSB 1066MHz
CFG[4:3]
Reserved
CFG6
0 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable
*
Reserved
CFG10 (PCIE Lookback enable)
(Default)11 = Normal Operation
10 = All Z Mode Enabled
00 = Reserved
01 = XOR Mode Enabled
*
0 = Enable
1 = Disable
*
CFG9
(PCIE Graphics Lane Reversal)
CFG[2:0] FSB Freq select
Reserved
ReservedCFG[15:14]
Strap Pin Table
ReservedCFG[18:17]
(Lane number in Order)
Others = Reserved
011 = FSB 667MHz
010 = FSB 800MHz
*
1 = Reverse Lane
0 = Reverse Lane,15->0, 14->1
1 = Enabled
0 = Normal Operation
0 = Disabled
*
0 = DMI x 2
*
*
1 = PCIE/SDVO are operating simu.
0 = Only PCIE or SDVO is operational.
*
1 = Normal Operation,Lane Number in order
1 = DMI x 4
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
CFG5 (DMI select)
CFG19 (DMI Lane Reversal)
CFG16 (FSB Dynamic ODT)
CFG6
CFG7 (Intel Management
Engine Crypto strap)
CFG20 (PCIE/SDVO concurrent)
CFG11
CFG[13:12] (XOR/ALLZ)
CFG8
C371 0.1U_0402_10V7KPM@C371 0.1U_0402_10V7KPM@
1 2
C673 0.1U_0402_10V7KGM@C673 0.1U_0402_10V7KGM@
1 2
C347 0.1U_0402_10V7KPM@C347 0.1U_0402_10V7KPM@
1 2
C349 0.1U_0402_10V7KPM@C349 0.1U_0402_10V7KPM@
1 2
C363 0.1U_0402_10V7KPM@C363 0.1U_0402_10V7KPM@
1 2
C669 0.1U_0402_10V7KGM@C669 0.1U_0402_10V7KGM@
1 2
C317 0.1U_0402_10V7KPM@C317 0.1U_0402_10V7KPM@
1 2
T72T72
R124 150_0402_1%
GM@
R124 150_0402_1%
GM@
1 2
R138
1.02K_0402_1%
R138
1.02K_0402_1%
12
T1T1
LVDS TV VGA
PCI-EXPRESS GRAPHICS
U26C
CANTIGA ES_FCBGA1329
GM@
LVDS TV VGA
PCI-EXPRESS GRAPHICS
U26C
CANTIGA ES_FCBGA1329
GM@
PEG_COMPI
T37
PEG_COMPO
T36
PEG_RX#_0
H44
PEG_RX#_1
J46
PEG_RX#_2
L44
PEG_RX#_3
L40
PEG_RX#_4
N41
PEG_RX#_5
P48
PEG_RX#_6
N44
PEG_RX#_7
T43
PEG_RX#_8
U43
PEG_RX#_9
Y43
PEG_RX#_10
Y48
PEG_RX#_11
Y36
PEG_RX#_12
AA43
PEG_RX#_13
AD37
PEG_RX#_14
AC47
PEG_RX#_15
AD39
PEG_RX_0
H43
PEG_RX_1
J44
PEG_RX_2
L43
PEG_RX_3
L41
PEG_RX_4
N40
PEG_RX_5
P47
PEG_RX_6
N43
PEG_RX_7
T42
PEG_RX_8
U42
PEG_RX_9
Y42
PEG_RX_10
W47
PEG_RX_11
Y37
PEG_RX_12
AA42
PEG_RX_13
AD36
PEG_RX_14
AC48
PEG_RX_15
AD40
PEG_TX#_0
J41
PEG_TX#_1
M46
PEG_TX#_2
M47
PEG_TX#_3
M40
PEG_TX#_4
M42
PEG_TX#_5
R48
PEG_TX#_6
N38
PEG_TX#_7
T40
PEG_TX#_8
U37
PEG_TX#_9
U40
PEG_TX#_10
Y40
PEG_TX#_11
AA46
PEG_TX#_12
AA37
PEG_TX#_13
AA40
PEG_TX#_14
AD43
PEG_TX#_15
AC46
PEG_TX_0
J42
PEG_TX_1
L46
PEG_TX_2
M48
PEG_TX_3
M39
PEG_TX_4
M43
PEG_TX_5
R47
PEG_TX_6
N37
PEG_TX_7
T39
PEG_TX_8
U36
PEG_TX_9
U39
PEG_TX_10
Y39
PEG_TX_11
Y46
PEG_TX_12
AA36
PEG_TX_13
AA39
PEG_TX_14
AD42
PEG_TX_15
AD46
L_BKLT_CTRL
L32
L_BKLT_EN
G32
L_CTRL_CLK
M32
L_CTRL_DATA
M33
L_DDC_CLK
K33
L_DDC_DATA
J33
L_VDD_EN
M29
LVDS_IBG
C44
LVDS_VBG
B43
LVDS_VREFH
E37
LVDS_VREFL
E38
LVDSA_CLK#
C41
LVDSA_CLK
C40
LVDSB_CLK#
B37
LVDSB_CLK
A37
LVDSA_DATA#_0
H47
LVDSA_DATA#_1
E46
LVDSA_DATA#_2
G40
LVDSA_DATA#_3
A40
LVDSA_DATA_0
H48
LVDSA_DATA_1
D45
LVDSA_DATA_2
F40
LVDSA_DATA_3
B40
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
H38
LVDSB_DATA#_2
G37
LVDSB_DATA#_3
J37
LVDSB_DATA_0
B42
LVDSB_DATA_1
G38
LVDSB_DATA_2
F37
LVDSB_DATA_3
K37
TVA_DAC
F25
TVB_DAC
H25
TVC_DAC
K25
TV_RTN
H24
TV_DCONSEL_0
C31
TV_DCONSEL_1
E32
CRT_BLUE
E28
CRT_GREEN
G28
CRT_RED
J28
CRT_IRTN
G29
CRT_DDC_CLK
H32
CRT_DDC_DATA
J32
CRT_HSYNC
J29
CRT_TVO_IREF
E29
CRT_VSYNC
L29
C375 0.1U_0402_10V7KPM@C375 0.1U_0402_10V7KPM@
1 2
T93T93
C303 0.1U_0402_10V7KPM@C303 0.1U_0402_10V7KPM@
1 2
R139
0_0402_5%
@
R139
0_0402_5%
@
C356 0.1U_0402_10V7KPM@C356 0.1U_0402_10V7KPM@
1 2
C358 0.1U_0402_10V7KPM@C358 0.1U_0402_10V7KPM@
1 2
R140
0_0402_5%
@
R140
0_0402_5%
@
R121 75_0402_5%GM@R121 75_0402_5%GM@
12
C372 0.1U_0402_10V7KPM@C372 0.1U_0402_10V7KPM@
1 2
C670 0.1U_0402_10V7KGM@C670 0.1U_0402_10V7KGM@
1 2
R640 0_0402_5%
GM@
R640 0_0402_5%
GM@
1 2
C368 0.1U_0402_10V7KPM@C368 0.1U_0402_10V7KPM@
1 2
C314 0.1U_0402_10V7KPM@C314 0.1U_0402_10V7KPM@
1 2
C271 0.1U_0402_10V7KPM@C271 0.1U_0402_10V7KPM@
1 2
C344 0.1U_0402_10V7KPM@C344 0.1U_0402_10V7KPM@
1 2
C354 0.1U_0402_10V7KPM@C354 0.1U_0402_10V7KPM@
1 2
C366 0.1U_0402_10V7KPM@C366 0.1U_0402_10V7KPM@
1 2
R127 75_0402_5%
GM@
R127 75_0402_5%
GM@
12
C663 0.1U_0402_10V7KGM@C663 0.1U_0402_10V7KGM@
1 2
T73T73
R123 150_0402_1%
GM@
R123 150_0402_1%
GM@
1 2
C311 0.1U_0402_10V7KPM@C311 0.1U_0402_10V7KPM@
1 2
R203 33_0402_1%GM@R203 33_0402_1%GM@
C343 0.1U_0402_10V7KPM@C343 0.1U_0402_10V7KPM@
1 2
C661 0.1U_0402_10V7KGM@C661 0.1U_0402_10V7KGM@
1 2
C325 0.1U_0402_10V7KPM@C325 0.1U_0402_10V7KPM@
1 2
R167 2.37K_0402_1%R167 2.37K_0402_1%
1 2
R204 33_0402_1%GM@R204 33_0402_1%GM@
C277 0.1U_0402_10V7KPM@C277 0.1U_0402_10V7KPM@
1 2
C346 0.1U_0402_10V7KPM@C346 0.1U_0402_10V7KPM@
1 2
C296 0.1U_0402_10V7KPM@C296 0.1U_0402_10V7KPM@
1 2
R213 10K_0402_5%R213 10K_0402_5%
1 2
C674 0.1U_0402_10V7KGM@C674 0.1U_0402_10V7KGM@
1 2
C662 0.1U_0402_10V7KGM@C662 0.1U_0402_10V7KGM@
1 2
C336 0.1U_0402_10V7KPM@C336 0.1U_0402_10V7KPM@
1 2
C352 0.1U_0402_10V7KPM@C352 0.1U_0402_10V7KPM@
1 2
C315 0.1U_0402_10V7KPM@C315 0.1U_0402_10V7KPM@
1 2
R122 75_0402_5%
GM@
R122 75_0402_5%
GM@
12
T94T94
C359 0.1U_0402_10V7KPM@C359 0.1U_0402_10V7KPM@
1 2
R132 150_0402_1%
GM@
R132 150_0402_1%
GM@
1 2
C373 0.1U_0402_10V7KPM@C373 0.1U_0402_10V7KPM@
1 2
R159 10K_0402_5%R159 10K_0402_5%
1 2
C351 0.1U_0402_10V7KPM@C351 0.1U_0402_10V7KPM@
1 2
C658 0.1U_0402_10V7KGM@C658 0.1U_0402_10V7KGM@
1 2
R163
49.9_0402_1%
R163
49.9_0402_1%
1 2
C367 0.1U_0402_10V7KPM@C367 0.1U_0402_10V7KPM@
1 2
C348 0.1U_0402_10V7KPM@C348 0.1U_0402_10V7KPM@
1 2
C322 0.1U_0402_10V7KPM@C322 0.1U_0402_10V7KPM@
1 2
C364 0.1U_0402_10V7KPM@C364 0.1U_0402_10V7KPM@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP
+3VS_DAC_BG
+3VS_DAC_CRT
+1.05VS_MPLL
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_DPLLA
+3VS
+3VS_DAC_BG
+3VS
+3VS_DAC_CRT
+1.8V_TXLVDS
+1.5VS_PEG_BG
+1.5VS
+1.05VS_PEGPLL
+1.05VS_A_SM
+VCCP
+1.05VS_A_SM_CK
+3VS_TVDAC
+1.5VS
+1.5VS_TVDAC
+1.5VS_QDAC
+1.05VS_PEGPLL
+1.05VS_HPLL
+1.8V_LVDS
+3VS_TVDAC
+1.5VS
+1.5VS_QDAC
+1.8V
+1.8V_LVDS
+1.8V_TXLVDS
+1.8V
+1.5V_SM_CK
+1.8V_TXLVDS
+3VS_HV
+VCC_PEG
+1.05VS_HPLL
+1.05VS_MPLL
+VCC_PEG
+VCCP
+1.05VS_PEGPLL
+VCCP
+V1.05VS_AXF
+1.5V
+1.5V_SM_CK
+1.05VS_DPLLA
+1.05VS_DPLLB
+VCCP
+VCCP
+VCCP
+3VS
+VCCP_D
+3VS_HV
+VCCP
+VCCP
+VCCP
+3VS
+VCC_DMI
+VCCP
+VCC_DMI
+V1.05VS_AXF
+1.5VS_TVDAC
+1.5VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Crestline GMCH (4/6)-VCC
Custom
11 52Friday, April 18, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Crestline GMCH (4/6)-VCC
Custom
11 52Friday, April 18, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
JITR1_LA-4141P
0.1
Crestline GMCH (4/6)-VCC
Custom
11 52Friday, April 18, 2008
2007/10/15 2008/10/15
Compal Electronics, Inc.
20 mils
40 mils
20mils
0316 add
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)
VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)
+1.05VS_DPLLA
+1.05VS_DPLLB: 64.8mA
(470UF*1, 0.1UF*1)
+1.05VS_HPLL: 24mA
(4.7UF*1, 0.1UF*1)
1.05VS_MPLL: 139.2mA
(22UF*1, 0.1UF*1)
+1.8V_TXLVDS: 118.8mA
(22UF*1, 1000PF*1)
+1.5VS_PEG_PLL: 50mA
(0.1UF*1)
+1.5VS_PEG_BG: 0.414mA
(0.1UF*1)
VCCA_SM:720mA
(22UF*2, 4.7UF*1, 1UF*1)
VCCA_SM_CK: 220mA
(22UF*1, 2.2UF*1, 0.1UF*1)
+3VS_TVDAC: 40mA
(0.1UF*1, 0.01UF*1 for
each DAC)
VCC_HDA: 50mA
(0.1UF*1)
VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)
VCCD_QDAC: 48.363mA
(0.1UF*1, 0.01UF*1)
1.8V_LVDS: 60.311111mA
(1UF*1)
VCC_AXF: 321.35mA
(10UF*1, 1UF*1)
VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)
VCC_DMI: 456mA
(0.1UF*1)
0316 add
R134
0_0603_5%
R134
0_0603_5%
12
C102
1U_0603_10V4Z
C102
1U_0603_10V4Z
1
2
R151
MCK3225151YZF 1210
GM@
R151
MCK3225151YZF 1210
GM@
1 2
C323
10U_0805_10V4Z
C323
10U_0805_10V4Z
1
2
C180
0_0402_5%
PM@
C180
0_0402_5%
PM@
R120
0_0603_5%
GM@
R120
0_0603_5%
GM@
1 2
R191
MCK3225151YZF 1210
GM@
R191
MCK3225151YZF 1210
GM@
1 2
R158
10_0402_5%
@R158
10_0402_5%
@
12
C608
0.1U_0402_16V4Z
C608
0.1U_0402_16V4Z
1
2
C637
0_0402_5%
PM@
C637
0_0402_5%
PM@
C639
10U_0805_10V4Z
GM@
C639
10U_0805_10V4Z
GM@
1
2
U26
PM
PM@
U26
PM
PM@
+
C605
220U_D2_4VY_R15M
+
C605
220U_D2_4VY_R15M
1
2
C649
0.1U_0402_16V4Z
C649
0.1U_0402_16V4Z
1
2
R117
0_0603_5%
GM@
R117
0_0603_5%
GM@
1 2
R166
0_0603_5%
R166
0_0603_5%
12
C94
0.47U_0402_6.3V6K
C94
0.47U_0402_6.3V6K
1
2
+
C339
220U_D2_4VM
+
C339
220U_D2_4VM
1
2
R208
0_0603_5%
GM@
R208
0_0603_5%
GM@
12
C221
10U_0805_10V4Z
GM@
C221
10U_0805_10V4Z
GM@
1
2
C629
10U_0805_10V4Z
C629
10U_0805_10V4Z
1
2
C631
1U_0603_10V4Z
C631
1U_0603_10V4Z
1
2
C181
0.022U_0402_16V7K
GM@
C181
0.022U_0402_16V7K
GM@
1
2
+
C747
220U_D2_4VM
@
+
C747
220U_D2_4VM
@
1
2
C627
10U_0805_10V4Z
C627
10U_0805_10V4Z
1
2
C603
2.2U_0603_6.3V4Z
C603
2.2U_0603_6.3V4Z
1
2
C206
0.1U_0402_16V4Z
GM@
C206
0.1U_0402_16V4Z
GM@
1
2
R496
0_0805_5%
R496
0_0805_5%
1 2
C353
10U_0805_10V4Z
C353
10U_0805_10V4Z
1
2
C195
0.1U_0402_16V4Z
GM@
C195
0.1U_0402_16V4Z
GM@
1
2
R495
0_0603_5%
R495
0_0603_5%
1 2
R115
0_0603_5%
GM@
R115
0_0603_5%
GM@
1 2
C226
10U_0805_10V4Z
GM@
C226
10U_0805_10V4Z
GM@
1
2
R202
0_0805_5%
R202
0_0805_5%
12
R473
MBK2012121YZF_0805
R473
MBK2012121YZF_0805
12
C214
1U_0603_10V4Z
C214
1U_0603_10V4Z
1
2
POWER
CRTPLLA LVDSA PEG
A SM
VTT
AXF
SM CK
VTTLF
LVDS D TV/CRT
TV
DMI PEG
HDA
A CK
HV
U26H
CANTIGA ES_FCBGA1329GM@
POWER
CRTPLLA LVDSA PEG
A SM
VTT
AXF
SM CK
VTTLF
LVDS D TV/CRT
TV
DMI PEG
HDA
A CK
HV
U26H
CANTIGA ES_FCBGA1329GM@
VTT_1
U13
VTT_2
T13
VTT_3
U12
VTT_4
T12
VTT_5
U11
VTT_6
T11
VTT_7
U10
VTT_8
T10
VTT_9
U9
VTT_10
T9
VTT_11
U8
VTT_12
T8
VTT_13
U7
VTT_14
T7
VTT_15
U6
VTT_16
T6
VTT_17
U5
VTT_18
T5
VTT_19
V3
VTT_20
U3
VTT_21
V2
VTT_22
U2
VTT_23
T2
VTT_24
V1
VTT_25
U1
VCC_AXF_1
B22
VCC_AXF_2
B21
VCC_AXF_3
A21
VCC_SM_CK_1
BF21
VCC_SM_CK_2
BH20
VCC_SM_CK_3
BG20
VCC_SM_CK_4
BF20
VCC_TX_LVDS
K47
VCC_HV_1
C35
VCC_HV_2
B35
VCC_HV_3
A35
VCC_PEG_1
V48
VCC_PEG_2
U48
VCC_PEG_3
V47
VCC_PEG_4
U47
VCC_PEG_5
U46
VCC_DMI_1
AH48
VCC_DMI_2
AF48
VCC_DMI_3
AH47
VCC_DMI_4
AG47
VTTLF1
A8
VTTLF2
L1
VTTLF3
AB2
VCCA_CRT_DAC_1
B27
VCCA_CRT_DAC_2
A26
VCCA_DAC_BG
A25
VSSA_DAC_BG
B25
VCCA_DPLLA
F47
VCCA_DPLLB
L48
VCCA_HPLL
AD1
VCCA_MPLL
AE1
VCCA_LVDS
J48
VSSA_LVDS
J47
VCCA_PEG_BG
AD48
VCCA_PEG_PLL
AA48
VCCA_SM_1
AR20
VCCA_SM_2
AP20
VCCA_SM_3
AN20
VCCA_SM_4
AR17
VCCA_SM_5
AP17
VCCA_SM_6
AN17
VCCA_SM_7
AT16
VCCA_SM_8
AR16
VCCA_SM_9
AP16
VCCA_SM_CK_1
AP28
VCCA_SM_CK_2
AN28
VCCA_SM_CK_3
AP25
VCCA_SM_CK_4
AN25
VCCA_SM_CK_5
AN24
VCCA_SM_CK_NCTF_1
AM28
VCCA_SM_CK_NCTF_2
AM26
VCCA_SM_CK_NCTF_3
AM25
VCCA_SM_CK_NCTF_4
AL25
VCCA_SM_CK_NCTF_5
AM24
VCCA_SM_CK_NCTF_6
AL24
VCCA_SM_CK_NCTF_7
AM23
VCCA_SM_CK_NCTF_8
AL23
VCCA_TV_DAC_1
B24
VCCA_TV_DAC_2
A24
VCC_HDA
A32
VCCD_TVDAC
M25
VCCD_QDAC
L28
VCCD_HPLL
AF1
VCCD_PEG_PLL
AA47
VCCD_LVDS_1
M38
VCCD_LVDS_2
L37
L17
BLM18PG121SN1D_0603
L17
BLM18PG121SN1D_0603
12
C198
10U_0805_10V4Z
GM@
C198
10U_0805_10V4Z
GM@
1
2
C171
0.1U_0402_16V4Z
GM@
C171
0.1U_0402_16V4Z
GM@
1
2
C300
1000P_0402_50V7K
C300
1000P_0402_50V7K
1
2
R157
0_0402_5%
R157
0_0402_5%
12
C628
0.1U_0402_16V4Z
C628
0.1U_0402_16V4Z
1
2
C265
4.7U_0805_10V4Z
C265
4.7U_0805_10V4Z
1
2
C301
0.1U_0402_16V4Z
C301
0.1U_0402_16V4Z
1
2
C638
0.022U_0402_16V7K
GM@
C638
0.022U_0402_16V7K
GM@
1
2
C180
0.022U_0402_16V7K
GM@
C180
0.022U_0402_16V7K
GM@
1
2
C795
10U_0805_10V4Z
C795
10U_0805_10V4Z
1
2
C208
1U_0402_6.3V4Z
GM@
C208
1U_0402_6.3V4Z
GM@
1
2
C310
10U_0805_10V4Z
GM@
C310
10U_0805_10V4Z
GM@
1
2
C207
0.1U_0402_16V4Z
C207
0.1U_0402_16V4Z
1
2
C299
0_0402_5%
PM@
C299
0_0402_5%
PM@
C1260.47U_0402_6.3V6K C1260.47U_0402_6.3V6K
1
2
R474
MBK2012121YZF_0805
R474
MBK2012121YZF_0805
12
R136
0_0603_5%
GM@
R136
0_0603_5%
GM@
12
C609
0.1U_0402_16V4Z
C609
0.1U_0402_16V4Z
1
2
C342
0.1U_0402_16V4Z
C342
0.1U_0402_16V4Z
1
2
R142
0_0603_5%
R142
0_0603_5%
12
C275
10U_0805_10V4Z
GM@
C275
10U_0805_10V4Z
GM@
1
2
R108
0_0805_5%
R108
0_0805_5%
1 2
C355
2.2U_0603_6.3V4Z
C355
2.2U_0603_6.3V4Z
1
2
C637
0.1U_0402_16V4Z
GM@
C637
0.1U_0402_16V4Z
GM@
1
2
C96
4.7U_0805_10V4Z
C96
4.7U_0805_10V4Z
1
2
C211
10U_0805_10V4Z
C211
10U_0805_10V4Z
1
2
C136
4.7U_0805_10V4Z
C136
4.7U_0805_10V4Z
1
2
C299
1000P_0402_50V7K
GM@
C299
1000P_0402_50V7K
GM@
1
2
C370
10U_0805_10V4Z
GM@
C370
10U_0805_10V4Z
GM@
1
2
C213
0.022U_0402_16V7K
GM@
C213
0.022U_0402_16V7K
GM@
1
2
C181
0_0402_5%
PM@
C181
0_0402_5%
PM@
C210
0.1U_0402_16V4Z
C210
0.1U_0402_16V4Z
1
2
D1
CH751H-40PT_SOD323-2
@D1
CH751H-40PT_SOD323-2
@
2 1
C237
0_0603_5%
PM@
C237
0_0603_5%
PM@
C206
0_0402_5%
PM@
C206
0_0402_5%
PM@
C618
0.47U_0402_6.3V6K
C618
0.47U_0402_6.3V6K
1
2
C337
1U_0603_10V4Z
C337
1U_0603_10V4Z
1
2
C278
0.1U_0402_16V4Z
GM@
C278
0.1U_0402_16V4Z
GM@
1
2
C312
0.1U_0402_16V4Z
GM@
C312
0.1U_0402_16V4Z
GM@
1
2
C194
1U_0402_6.3V4Z
C194
1U_0402_6.3V4Z
1
2
C604
2.2U_0603_6.3V4Z
C604
2.2U_0603_6.3V4Z
1
2
R137
0_0603_5%
GM@
R137
0_0603_5%
GM@
12
C87
10U_0805_10V4Z
C87
10U_0805_10V4Z
1
2
C611
0.47U_0402_6.3V6K
C611
0.47U_0402_6.3V6K
1
2
C237
1U_0603_10V4Z
GM@
C237
1U_0603_10V4Z
GM@
1
2
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