ADSP-BF561技术手册：双核Blackfin处理器详解

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"ADSP-BF561手册是ADI公司Blackfin系列的一款高性能嵌入式处理器的技术文档，详细介绍了BF561芯片的特性和使用方法。该处理器具备双核对称多处理能力，每核心拥有强大的计算单元，并集成了丰富的外设接口。" 在ADSP-BF561处理器中，主要特点包括： 1. **双核对称多处理器（Symmetric Multiprocessor）**：BF561内含两个600MHz的高性能Blackfin处理器核心，可提供高处理能力，适合并行处理和负载均衡。 2. **内存架构**：集成328Kbytes的片上内存，包括L1和L2缓存，以及Boot ROM、Program Access Bus (PAB)、External Access Bus (EAB)和Data Access Bus (DAB)等，优化了数据访问速度和系统响应。 3. **计算单元**：每个Blackfin核心配备两个16位MAC（乘累加器）、两个40位ALU（算术逻辑单元）、四个8位视频ALU和一个40位移位器，增强了数字信号处理能力。 4. **编程友好性**：采用RISC-like指令集，简化编程并支持编译器友好的设计。 5. **高级调试与性能监控**：提供了先进的调试、追踪和性能监测功能，便于开发和优化应用。 6. **宽范围工作电压**：适应多种操作环境，具体条件可见第20页的Operating Conditions部分。 7. **封装选项**：提供256-ball CSP_BGA（两种尺寸）和297-ball PBGA封装，满足不同应用需求。 8. **外设接口**： - 双12通道DMA控制器，支持24个外围设备的DMA传输。 - 2个内存到内存的DMA。 - VOLTA（电压调节器）和REGULA（稳压器）用于电源管理。 - 外部端口、FLASH/SDRAM控制。 - 32位GPIO、SPI、SPORT0、SPORT1、UART、IrDA、多个DMA控制器和PPI接口。 - IRQCONTROL（中断控制器）和WATCHDOG TIMER（看门狗定时器），确保系统稳定运行。 - L1和L2 SRAM内存层次结构，128KBYTES的L2 SRAM作为扩展存储。 ADSP-BF561的这些特性使其成为需要高效能计算和复杂信号处理任务的理想选择，例如音频、视频编码和解码、图像处理、网络和通信应用。通过理解手册中的内容，开发者能够充分利用BF561的硬件资源，优化程序设计，实现高效的系统解决方案。

ADSP-BF561

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(e.g., for frame capture). The ADSP-BF561 processors control

when to read from the video source(s). PPI_FS1 is an HSYNC

output and PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

• Active video only mode

• Vertical blanking only mode

• Entire field mode

Active Video Only Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in the PPI_COUNT register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1.

DYNAMIC POWER MANAGEMENT

The ADSP-BF561 provides four power management modes and

one power management state, each with a different perfor-

mance/power profile. In addition, dynamic power management

provides the control functions to dynamically alter the proces-

sor core supply voltage, further reducing power dissipation.

Control of clocking to each of the ADSP-BF561 peripherals also

reduces power consumption. See Table 3 for a summary of the

power settings for each mode.

Table 3. Power Settings

Mode/State PLL

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Core

Power

Full-On

Active

Sleep

Deep Sleep

Hibernate

Enabled

Enabled/

Disabled

Enabled

Disabled

Yes

–

Enabled

Disabled

Enabled

Disabled

Off

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the default execution state in which maximum performance

can be achieved. The processor cores and all enabled peripherals

run at full speed.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the full-on mode is

entered. DMA access is available to appropriately configured L1

and L2 memories.

In the active mode, it is possible to disable the PLL through the

PLL control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces power dissipation by disabling the

clock to the processor core (CCLK). The PLL and system clock

(SCLK), however, continue to operate in this mode. Typically an

external event will wake up the processor. When in the sleep

mode, assertion of wakeup will cause the processor to sense the

value of the BYPASS bit in the PLL control register (PLL_CTL).

When in the sleep mode, system DMA access is only available to

external memory, not to L1 or on-chip L2 memory.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes power savings by disabling the

clocks to the processor cores (CCLK) and to all synchronous

peripherals (SCLK). Asynchronous peripherals will not be able

to access internal resources or external memory. This powered-

down mode can only be exited by assertion of the reset pin

(RESET). If BYPASS is disabled, the processor will transition to

the full-on mode. If BYPASS is enabled, the processor will tran-

sition to the active mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all

the synchronous peripherals (SCLK). The internal voltage

Rev. E | Page 11 of 64 | September 2009

--------------------- -------------------------- -----------

ADSP-BF561

regulator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V

DDINT

) to 0 V to provide the lowest static power dissipation.

Any critical information stored internally (memory contents,

device prior to removing power if the processor state is to be

preserved. Since V

DDEXT

is still supplied in this mode, all of the

external pins three-state, unless otherwise specified. This allows

other devices that may be connected to the processor to have

power still applied without drawing unwanted current. The

internal supply regulator can be woken up by asserting the

RESET pin.

Power Savings

As shown in Table 4, the ADSP-BF561 supports two different

power domains. The use of multiple power domains maximizes

flexibility, while maintaining compliance with industry stan-

dards and conventions. By isolating the internal logic of the

ADSP-BF561 into its own power domain, separate from the I/O,

the processor can take advantage of Dynamic Power Manage-

ment, without affecting the I/O devices. There are no

sequencing requirements for the various power domains.

Table 4. ADSP-BF561 Power Domains

Power Domain V

Range

All internal logic V

DDINT

I/O V

DDEXT

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

NOM

is the duration running at f

CCLKNOM

RED

is the duration running at f

CCLKRED

The percent power savings is calculated as:

% power savings = (1 – power savings factor) × 100%

VOLTAGE REGULATION

The ADSP-BF561 processor provides an on-chip voltage regula-

tor that can generate appropriate V

DDINT

voltage levels from the

DDEXT

supply. See Operating Conditions on Page 20 for regula-

tor tolerances and acceptable V

DDEXT

ranges for specific models.

Figure 4 shows the typical external components required to

complete the power management system. The regulator con-

trols the internal logic voltage levels and is programmable with

the voltage regulator control register (VR_CTL) in increments

of 50 mV. To reduce standby power consumption, the internal

voltage regulator can be programmed to remove power to the

processor core while keeping I/O power (V

DDEXT

) supplied. While

in the hibernate state, V

DDEXT

can still be applied, thus eliminating

the need for external buffers. The voltage regulator can be acti-

vated from this power-down state by asserting RESET, which

will then initiate a boot sequence. The regulator can also be dis-

abled and bypassed at the user’s discretion.

The internal voltage regulation feature is not available on any of

the 600 MHz speed grade models or automotive grade models.

External voltage regulation is required to ensure correct opera-

tion of these parts at 600 MHz.

DDEXT

SET OF DECOUPLING

(LOW-INDUCTANCE)

CAPACITORS

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in dynamic power dissipation, while

reducing the voltage by 25% reduces dynamic power dissipation

by more than 40%. Further, these power savings are additive, in

that if the clock frequency and supply voltage are both reduced,

the power savings can be dramatic.

100µF

DDINT

OUT

100µF

OUT

GND

SHORT AND LOW-

INDUCTANCE WIRE

DDEXT

100µF

100nF

ZHCS1000

10µH

FDS9431A

The dynamic power management feature of the ADSP-BF561

allows both the processor’s input voltage (V

DDINT

) and clock fre-

10µF

LOW ESR

quency (f

CCLK

) to be dynamically controlled.

The savings in power dissipation can be modeled using the

power savings factor and % power savings calculations.

The power savings factor is calculated as:

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

power savings factor

CCLKRED

DDINTRED

RED

 









×=

 

CCLKNOM

DDINTNOM

NOM

Figure 4. Voltage Regulator Circuit

where the variables in the equations are:

CCLKNOM

is the nominal core clock frequency

CCLKRED

is the reduced core clock frequency

DDINTNOM

is the nominal internal supply voltage

DDINTRED

is the reduced internal supply voltage

Voltage Regulator Layout Guidelines

Regulator external component placement, board routing, and

bypass capacitors all have a significant effect on noise injected

into the other analog circuits on-chip. The VROUT1–0 traces

and voltage regulator external components should be consid-

ered as noise sources when doing board layout and should not

be routed or placed near sensitive circuits or components on the

Rev. E | Page 12 of 64 | September 2009

ADSP-BF561

board. All internal and I/O power supplies should be well

bypassed with bypass capacitors placed as close to the

ADSP-BF561 processors as possible.

For further details on the on-chip voltage regulator and related

board design guidelines, see the Switching Regulator Design

Considerations for ADSP-BF533 Blackfin Processors (EE-228)

applications note on the Analog Devices web site (www.ana-

log.com)—use site search on “EE-228”.

CLOCK SIGNALS

The ADSP-BF561 processor can be clocked by an external crys-

tal, a sine wave input, or a buffered, shaped clock derived from

an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF561 processor includes an

on-chip oscillator circuit, an external crystal may be used. For

fundamental frequency operation, use the circuit shown in

Figure 5. A parallel-resonant, fundamental frequency, micro-

processor-grade crystal is connected across the CLKIN and

XTAL pins. The on-chip resistance between CLKIN and the

XTAL pin is in the 500 kΩ range. Further parallel resistors are

typically not recommended. The two capacitors and the series

resistor shown in Figure 5 fine tune the phase and amplitude of

the sine frequency. The capacitor and resistor values shown in

Figure 5 are typical values only. The capacitor values are depen-

dent upon the crystal manufacturer’s load capacitance

recommendations and the physical PCB layout. The resistor

value depends on the drive level specified by the crystal manu-

facturer. System designs should verify the customized values

based on careful investigation on multiple devices over the

allowed temperature range.

A third-overtone crystal can be used at frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 5.

As shown in Figure 6, the core clock (CCLK) and system

peripheral clock (SCLK) are derived from the input clock

(CLKIN) signal. An on-chip PLL is capable of multiplying the

CLKIN signal by a user-programmable 0.5× to 64× multiplica-

tion factor. The default multiplier is 10×, but it can be modified

by a software instruction sequence. On the fly frequency

changes can be effected by simply writing to the PLL_DIV

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

CLKOUT

CLKIN

XTAL

18pF* 18pF*

FOR OVERTONE

OPERATION ONLY

DDEXT

TO PLL CIRCUITRY

Blackfin

700O

0O*

1MO

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

Figure 5. External Crystal Connections

“FINE” ADJUSTMENT “COARSE” ADJUSTMENT

REQUIRES PLL SEQUENCING ON-THE-FLY

PLL

0.5u

to 64u

÷1 to 15

÷1, 2,4,8

VCO

CCLK

CLKIN

SCLK

SCLK d

CCLK

SCLK d

133 MHz

Figure 6. Frequency Modification Methods

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 5 illustrates typical system clock ratios.

Table 5. Example System Clock Ratios

Example Frequency

Ratios (MHz)

Signal Name Divider Ratio

SSEL3–0 VCO/SCLK VCO SCLK

0001 1:1 100 100

0110 6:1 300 50

1010 10:1 500 50

The maximum frequency of the system clock is f

SCLK

. Note that

the divisor ratio must be chosen to limit the system clock fre-

quency to its maximum of f

SCLK

. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the

appropriate values to the PLL divisor register (PLL_DIV).

Rev. E | Page 13 of 64 | September 2009

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