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首页PCI Express 4.0: 高性能串行接口技术详解
PCI Express 4.0: 高性能串行接口技术详解
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"PCI_Express_Base_4.0r0.7_November-11-2016-英文原版.pdf"
PCI Express(PCIe)是一种高速、通用的I/O接口标准,用于未来的各种计算和通信平台。在保持关键的PCI特性,如使用模型、加载-存储架构和软件接口的同时,它摒弃了并行总线实现,转而采用高度可扩展的全串行接口。PCIe利用点对点互连、基于交换的技术以及分组化协议的优势,提供了新的性能水平和功能。其中,电源管理、服务质量(QoS)、热插拔/热交换支持、数据完整性和错误处理是PCI Express所支持的一些高级特性。
在4.0版本中,PCIe协议进一步提升了带宽和性能,以满足不断增长的高速数据传输需求。然而,读者需要注意的是,文档中可能存在的错误(errata)和工程变更通知(ECN)是独立于新规格内容开发和发布的流程。如果有任何已批准和发布的errata或ECN,它们将在未来修订版的规格书中被包含。
文档中提到了HotPlug(热插拔)的章节(第6章和第7章),表示正在考虑对其进行重大修订,这些修订可能通过errata、ECN或新的规格内容来实现,旨在尊重当前的实现实践。由于有大量的新内容或修改,0.7版本的交叉引用可能存在不准确的问题,这将在0.9版本中得到修复。
此外,扩展可调整大小的BARE CN在当前文档中被遗漏,这将在0.9版本中得到修正。Vital Product Data(关键产品数据)计划从传统的PCI规格中导入到0.9版本的文档中。同时,从传统PCI、PCI-PM规范、PCI到PCI桥接器规范、SR-IOV(单根I/O虚拟化)和ATS(原子事务扩展)规范中融入的材料也是内容的一部分。
PCI Express 4.0标准是一个不断演进的技术,旨在提供更高的数据传输速率、增强的电源管理和服务质量,以及改进的硬件交互功能,以适应不断变化的计算环境和需求。随着技术的发展,规范会不断更新和完善,以确保与实际的实现和市场需求保持同步。
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
16
7.27.2 ARI Capability Register (Offset 04h) .................................................................. 965
7.27.3 ARI Control Register (Offset 06h) ...................................................................... 966
7.28 DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ................................................... 967
7.28.1 DPA Extended Capability Header (Offset 00h) .................................................. 967
7.28.2 DPA Capability Register (Offset 04h) ................................................................ 968
7.28.3 DPA Latency Indicator Register (Offset 08h) ..................................................... 969
7.28.4 DPA Status Register (Offset 0Ch) ....................................................................... 969
7.28.5 DPA Control Register (Offset 0Eh) .................................................................... 970
7.28.6 DPA Power Allocation Array ............................................................................. 970
7.29 LATENCY TOLERANCE REPORTING (LTR) CAPABILITY ............................................... 971
7.29.1 LTR Extended Capability Header (Offset 00h) ................................................... 971
7.29.2 Max Snoop Latency Register (Offset 04h) .......................................................... 972
7.29.3 Max No-Snoop Latency Register (Offset 06h) .................................................... 973
7.30 TPH REQUESTER CAPABILITY ..................................................................................... 973
7.30.1 TPH Requester Extended Capability Header (Offset 00h) ................................. 974
7.30.2 TPH Requester Capability Register (Offset 04h) ................................................ 975
7.30.3 TPH Requester Control Register (Offset 08h) .................................................... 976
7.30.4 TPH ST Table (Starting from Offset 0Ch) .......................................................... 977
7.31 M-PCIE EXTENDED CAPABILITY ................................................................................. 978
7.31.1 M-PCIe Extended Capability Header (Offset 00h) ............................................. 979
7.31.2 M-PCIe Capabilities Register (Offset 04h) ......................................................... 980
7.31.3 M-PCIe Control Register (Offset 08h) ................................................................ 981
7.31.4 M-PCIe Status Register (Offset 0Ch) .................................................................. 981
7.31.5 M-PCIe LANE Error Status Register (Offset 10h) ............................................. 983
7.31.6 M-PCIe Phy Control Address Register (Offset 14h) ........................................... 983
7.31.7 M-PCIe Phy Control Data Register (Offset 18h) ............................................... 984
7.32 PASID EXTENDED CAPABILITY STRUCTURE ............................................................... 986
7.32.1 PASID Extended Capability Header (Offset 00h) .............................................. 986
7.32.2 PASID Capability Register (Offset 04h) ............................................................. 987
7.32.3 PASID Control Register (Offset 06h) ................................................................. 988
7.33 LNR EXTENDED CAPABILITY ...................................................................................... 989
7.33.1 LNR Extended Capability Header (Offset 00h) .................................................. 989
7.33.2 LNR Capability Register (Offset 04h) ................................................................. 990
7.33.3 LNR Control Register (Offset 04h) ..................................................................... 991
7.34 DPC EXTENDED CAPABILITY ...................................................................................... 991
7.34.1 DPC Extended Capability Header (Offset 00h) .................................................. 993
7.34.2 DPC Capability Register (Offset 04h) ................................................................ 993
7.34.3 DPC Control Register (Offset 06h)..................................................................... 995
7.34.4 DPC Status Register (Offset 08h) ....................................................................... 997
7.34.5 DPC Error Source ID Register (Offset 0Ah) ...................................................... 998
7.34.6 RP PIO Status Register (Offset 0Ch) .................................................................. 999
7.34.7 RP PIO Mask Register (Offset 10h) .................................................................. 1000
7.34.8 RP PIO Severity Register (Offset 14h) .............................................................. 1001
7.34.9 RP PIO SysError Register (Offset 18h) ............................................................ 1002
7.34.10 RP PIO Exception Register (Offset 1Ch) .......................................................... 1003
7.34.11 RP PIO Header Log Register (Offset 20h) ....................................................... 1004
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
17
7.34.12 RP PIO ImpSpec Log Register (Offset 30h) ..................................................... 1004
7.34.13 RP PIO TLP Prefix Log Register (Offset 34h) .................................................. 1005
7.35 PRECISION TIME MANAGEMENT (PTM) CAPABILITY ................................................ 1006
7.35.1 PTM Extended Capability Header (Offset 00h) ................................................ 1007
7.35.2 PTM Capability Register (Offset 04h) .............................................................. 1007
7.35.3 PTM Control Register (Offset 08h)................................................................... 1008
7.36 L1 PM SUBSTATES EXTENDED CAPABILITY .............................................................. 1010
7.36.1 L1 PM Substates Extended Capability Header (Offset 00h) ............................ 1010
7.36.2 L1 PM Substates Capabilities Register (Offset 04h) ........................................ 1011
7.36.3 L1 PM Substates Control 1 Register (Offset 08h) ............................................ 1013
7.36.4 L1 PM Substates Control 2 Register (Offset 0Ch) ............................................ 1015
7.37 FUNCTION READINESS STATUS (FRS) QUEUING EXTENDED CAPABILITY ................. 1016
7.37.1 Function Readiness Status (FRS) Queuing Extended Capability Header (Offset
00h) 1017
7.37.2 FRS Queuing Capability Register (Offset 04h) ................................................ 1017
7.37.3 FRS Queuing Status Register (Offset 08h)........................................................ 1018
7.37.4 FRS Queuing Control Register (Offset 0Ah) .................................................... 1019
7.37.5 FRS Message Queue Register (Offset 0Ch) ...................................................... 1019
7.38 READINESS TIME REPORTING EXTENDED CAPABILITY .............................................. 1021
7.38.1 Readiness Time Reporting Extended Capability Header (Offset 00h) ............. 1023
7.38.2 Readiness Time Reporting 1 (Offset 04h) ......................................................... 1024
7.38.3 Readiness Time Reporting 2 (Offset 08h) ......................................................... 1025
7.39 DESIGNATED VENDOR-SPECIFIC EXTENDED CAPABILITY (DVSEC) ......................... 1025
7.39.1 Designated Vendor-Specific Extended Capability Header (Offset 00h) ........... 1026
7.39.2 Designated Vendor-Specific Header 1 (Offset 04h) ......................................... 1027
7.39.3 Designated Vendor-Specific Header 2 (Offset 08h) ......................................... 1028
7.40 PHYSICAL LAYER 16.0 GT/S EXTENDED CAPABILITY ................................................ 1028
7.40.1 Physical Layer 16.0 GT/s Extended Capability Header (Offset 00h) ............... 1028
7.40.2 16.0 GT/s Capabilities Register (Offset 04h) .................................................... 1029
7.40.3 16.0 GT/s Control Register (Offset 08h) ........................................................... 1029
7.40.4 16.0 GT/s Status Register (Offset 0Ch) ............................................................. 1029
7.40.5 16.0 GT/s Local Data Parity Mismatch Status Register (Offset 10h) ............... 1030
7.40.6 16.0 GT/s First Retimer Data Parity Mismatch Status Register (Offset 14h) .. 1031
7.40.7 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (Offset 18h)
1032
7.40.8 16.0 GT/s Control Register ............................................................................... 1033
7.40.9 16.0 GT/s Lane Equalization Control Register (Offset 20h) ............................ 1033
7.41 LANE MARGINING AT THE RECEIVER EXTENDED CAPABILITY .................................. 1035
7.41.1 Margining Extended Capability Header (Offset 00h) ...................................... 1036
7.41.2 Margining Port Capabilities Register (Offset 04h) .......................................... 1037
7.41.3 Margining Port Status Register (Offset 06h) .................................................... 1037
7.41.4 Margining Lane Control Register (Offset 08h) ................................................ 1038
7.41.5 Margining Lane Status Register (Offset 0Ah) ................................................... 1039
8 M-PCIE LOGICAL SUB-BLOCK ............................................................................... 1044
8.1 PHY REQUIREMENTS ................................................................................................. 1046
8.2 CONFIGURATION ........................................................................................................ 1047
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
18
8.2.1 Link Discovery and Configuration........................................................................ 1047
8.2.2 Attributes ............................................................................................................... 1048
8.2.3 Remote Register Access Protocol (RRAP): ........................................................... 1061
8.3 SYMBOL ENCODING, FRAMING AND SCRAMBLING .................................................... 1074
8.3.1 8b/10b Decode Rules ............................................................................................ 1074
8.3.2 Framing and Application of Symbols to LANES ................................................... 1074
8.3.3 Data Scrambling ................................................................................................... 1075
8.4 LINK INITIALIZATION AND TRAINING ......................................................................... 1075
8.4.1 Training Sequence (TS) Ordered Sets................................................................... 1076
8.4.2 Electrical Idle ........................................................................................................ 1082
8.4.3 EIEOS for M-PCIe ................................................................................................ 1082
8.4.4 Lane Polarity Inversion ........................................................................................ 1082
8.4.5 Fast Training Sequence (FTS) .............................................................................. 1082
8.4.6 LINK Data RATE .................................................................................................. 1083
8.4.7 LINK Width ........................................................................................................... 1083
8.4.8 LANE-to-LANE De-skew ...................................................................................... 1083
8.4.9 LINK Training and Status State Machine (LTSSM) ............................................. 1083
8.4.10 Entry to HIBERN8 ............................................................................................ 1105
8.5 RECEIVER ERROR ....................................................................................................... 1105
8.6 CLOCK TOLERANCE COMPENSATION ......................................................................... 1106
8.7 DYNAMIC LINK BANDWIDTH MANAGEMENT ........................................................... 1106
8.7.1 LINK Rate Series and Speed Management ........................................................... 1107
8.7.2 LINK Width Management ..................................................................................... 1107
8.7.3 Dynamic LINK Re-Configuration ......................................................................... 1107
8.8 M-PHY REGISTERS ................................................................................................... 1111
8.8.1 M-PHY Capability Registers ................................................................................. 1111
8.8.2 M-PHY Configuration Attributes .......................................................................... 1118
9 ELECTRICAL SUB-BLOCK........................................................................................ 1120
9.1 ELECTRICAL SPECIFICATION ORGANIZATION............................................................. 1120
9.2 INTEROPERABILITY CRITERIA .................................................................................... 1120
9.2.1 Data Rates ............................................................................................................. 1120
9.2.2 Refclk Architectures .............................................................................................. 1120
9.3 TRANSMITTER SPECIFICATION ................................................................................... 1120
9.3.1 Measurement Setup for Characterizing Transmitters ........................................... 1120
9.3.2 Voltage Level Definitions ...................................................................................... 1122
9.3.3 Tx Voltage Parameters ......................................................................................... 1123
9.3.4 Transmitter Margining ......................................................................................... 1132
9.3.5 Tx Jitter Parameters ............................................................................................. 1133
9.3.6 Data Rate Dependent Parameters ........................................................................ 1140
9.3.7 Tx and Rx Return Loss .......................................................................................... 1144
9.3.8 Transmitter PLL Bandwidth and Peaking ............................................................ 1145
9.3.9 Data Rate Independent Tx Parameters ................................................................. 1146
9.4 RECEIVER SPECIFICATIONS ........................................................................................ 1147
9.4.1 Receiver Stressed Eye Specification ..................................................................... 1147
9.4.2 Stressed Eye Test ................................................................................................... 1153
9.4.3 Common Receiver Parameters ............................................................................. 1161
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
19
9.4.4 Lane Margining at the Receiver ........................................................................... 1164
9.4.5 Low Frequency and Miscellaneous Signaling Requirements ............................... 1166
9.5 CHANNEL TOLERANCING ........................................................................................... 1169
9.5.1 Channel Compliance Testing ................................................................................ 1169
9.6 REFCLK SPECIFICATIONS ........................................................................................... 1179
9.6.1 Refclk Test Setup ................................................................................................... 1179
9.6.2 REFCLK AC Specifications .................................................................................. 1180
9.6.3 Data Rate Independent Refclk Parameters ........................................................... 1183
9.6.4 Refclk Architectures Supported ............................................................................. 1184
9.6.5 Filtering Functions Applied to Raw Data ............................................................. 1184
9.6.6 Common Refclk Rx Architecture (CC) .................................................................. 1186
9.6.7 Jitter Limits for Refclk Architectures .................................................................... 1189
10 SINGLE ROOT I/O VIRTUALIZATION AND SHARING ...................................... 1191
10.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1191
10.1.1 PCI Technologies Interoperability ................................................................... 1203
10.2 INITIALIZATION AND RESOURCE ALLOCATION .......................................................... 1204
10.2.1 SR-IOV Resource Discovery ............................................................................. 1204
10.2.2 Reset Mechanisms ............................................................................................. 1209
10.2.3 IOV Re-initialization and Reallocation ............................................................ 1209
10.2.4 VF Migration .................................................................................................... 1209
10.3 CONFIGURATION ........................................................................................................ 1213
10.3.1 Overview ........................................................................................................... 1213
10.3.2 Configuration Space ......................................................................................... 1213
10.3.3 SR-IOV Extended Capability ............................................................................ 1213
10.3.4 PF/VF Configuration Space Header ................................................................ 1232
10.3.5 PCI Express Capability ..................................................................................... 1237
10.3.6 PCI Standard Capabilities ................................................................................ 1248
10.3.7 PCI Express Extended Capabilities .................................................................. 1249
10.4 ERROR HANDLING ..................................................................................................... 1258
10.4.1 Baseline Error Reporting .................................................................................. 1258
10.4.2 Advanced Error Reporting ................................................................................ 1259
10.5 INTERRUPTS ............................................................................................................... 1265
10.5.1 Interrupt Mechanisms ....................................................................................... 1265
10.6 POWER MANAGEMENT ............................................................................................... 1266
10.6.1 VF Device Power Management States .............................................................. 1266
10.6.2 PF Device Power Management States .............................................................. 1267
10.6.3 Link Power Management State ......................................................................... 1268
10.6.4 VF Power Management Capability .................................................................. 1268
10.6.5 VF EmergencyPower Reduction State .............................................................. 1269
11 ATS SPECIFICATION .................................................................................................. 1271
11.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1271
11.1.1 Address Translation Services (ATS) Overview ................................................. 1273
11.1.2 Page Request Interface Extension .................................................................... 1278
11.1.3 Process Address Space ID (PASID) ................................................................. 1280
11.2 ATS TRANSLATION SERVICES ................................................................................... 1281
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
20
11.2.1 Memory Requests with Address Type ............................................................... 1281
11.2.2 Translation Requests ......................................................................................... 1282
11.2.3 Translation Completion .................................................................................... 1285
11.2.4 Completions with Multiple Translations ........................................................... 1292
11.3 ATS INVALIDATION ................................................................................................... 1294
11.3.1 Invalidate Request ............................................................................................. 1294
11.3.2 Invalidate Completion ....................................................................................... 1295
11.3.3 Invalidate Completion Semantics ..................................................................... 1297
11.3.4 Request Acceptance Rules................................................................................. 1298
11.3.5 Invalidate Flow Control .................................................................................... 1298
11.3.6 Invalidate Ordering Semantics ......................................................................... 1299
11.3.7 Implicit Invalidation Events .............................................................................. 1300
11.3.8 PASID TLP Prefix and Global Invalidate ........................................................ 1301
11.4 PAGE REQUEST SERVICES .......................................................................................... 1302
11.4.1 Page Request Message ...................................................................................... 1303
11.4.2 Page Request Group Response Message .......................................................... 1307
11.5 CONFIGURATION ........................................................................................................ 1309
11.5.1 ATS Extended Capability Structure .................................................................. 1309
11.5.2 Page Request Extended Capability Structure ................................................... 1312
A. ISOCHRONOUS APPLICATIONS ................................................................................. 1319
A.1. INTRODUCTION .......................................................................................................... 1319
A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ......................................... 1321
A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ........................... 1322
A.2.2. Isochronous Payload Size ................................................................................. 1323
A.2.3. Isochronous Bandwidth Allocation ................................................................... 1323
A.2.4. Isochronous Transaction Latency ..................................................................... 1324
A.2.5. An Example Illustrating Isochronous Parameters ............................................ 1325
A.3. ISOCHRONOUS TRANSACTION RULES ......................................................................... 1326
A.4. TRANSACTION ORDERING .......................................................................................... 1326
A.5. ISOCHRONOUS DATA COHERENCY ............................................................................. 1326
A.6. FLOW CONTROL ......................................................................................................... 1327
A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ..................................................... 1327
A.7.1. Isochronous Bandwidth of PCI Express Links.................................................. 1327
A.7.2. Isochronous Bandwidth of Endpoints ............................................................... 1327
A.7.3. Isochronous Bandwidth of Switches ................................................................. 1327
A.7.4. Isochronous Bandwidth of Root Complex......................................................... 1328
A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ................................................... 1328
A.8.1. An Endpoint as a Requester .............................................................................. 1328
A.8.2. An Endpoint as a Completer ............................................................................. 1328
A.8.3. Switches............................................................................................................. 1329
A.8.4. Root Complex .................................................................................................... 1330
B. SYMBOL ENCODING .................................................................................................... 1331
C. PHYSICAL LAYER APPENDIX .................................................................................... 1340
C.1. 8B/10B DATA SCRAMBLING EXAMPLE ....................................................................... 1340
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