XADCWizard v3.3 IP Guide: Design and Implementation Tutorial

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本资源是一份名为"pg091-xadc-wiz.pdf"的教程与笔记习题，专注于Xilinx的IP产品指南，具体是针对XADC Wizard v3.3。XADC Wizard 是一款用于设计Xilinx特定应用数字信号转换器（XADC）的工具，它在Vivado Design Suite中被集成。该指南发布于2016年10月5日，适用于操作系统要求，详细介绍了产品的功能、应用、安装步骤、设计流程以及一个示例设计。 **章节一：概述** - 提供了操作系统需求，确保用户在使用XADC Wizard之前具备兼容的系统环境。 - 通过"FeatureSummary"部分，总结了XADC Wizard的主要特性和优势，可能包括高精度数据采集、低功耗设计以及多通道支持等。 - "Applications"部分阐述了XADC Wizard的应用场景，如电源监控、环境监测、工业自动化等。 **章节二：产品规格** - 功能概述部分深入解析XADC的核心功能，包括其作为模拟到数字转换器的工作原理。 - "Standards"列出了遵循的行业标准，如数字接口协议（如AXI4-Lite）、模拟输入标准等。 - "Performance"和"ResourceUtilization"提供了关于性能指标和硬件资源占用的信息，有助于设计师了解核心在实际项目中的表现。 - "PortDescriptions"详细描述了各种接口的用途，包括输入/输出端口、控制信号和配置寄存器。 - 专门章节解释了XADC Wizard的寄存器空间组织，包括AXI4-Lite接口下的本地寄存器组、中断控制器寄存器组和硬宏寄存器（DRP寄存器）组。 **章节三：设计流程** - "Clocking"和"Resets"讲解了时钟管理和复位策略在设计XADC核心时的重要性。 - "ProtocolDescription"部分阐述了与XADC Wizard交互的协议规范，包括如何配置和操作核心以达到预期的性能。 **章节四：设计流程步骤** - "CustomizingandGeneratingtheCore"涉及如何根据项目需求定制和生成核心IP。 - "ConstrainingtheCore"说明了如何在设计流程中对XADC进行约束，以确保满足项目要求。 - "Simulation"强调了模拟验证在设计过程中的作用，可能包含使用行为模型或仿真工具。 - "SynthesisandImplementation"涵盖了综合和实施阶段，指导用户如何将设计转化为硬件实现。 **章节五：示例设计** - "Directo"可能指的是设计者可以直接参考的示例项目，展示了如何将XADC Wizard应用于实际电路设计中，帮助新用户理解和掌握工具的使用。这份文档是为希望利用XADC Wizard进行数字信号采集的工程师提供的实用资源，从基础安装、配置到高级设计技巧，全面覆盖了整个设计流程。通过阅读并遵循其中的指导，设计师能够更有效地利用Xilinx的XADC IP来构建高性能的系统。

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PG091 October 5, 2016

Chapter 2: Product Specification

Performance

If you enable averaging of the channel, data capture rate is reduced depending on the

averaging selected. Choose the appropriate value to match your requirement. Analog Input

noise from the supply or board can deviate from the expected 12-bit digital output.

Maximum Frequencies

Note: Maximum frequency numbers for Zynq

-7000 All Programmable SoC devices are expected to

be similar to 7 series device numbers.

The maximum s_axi_aclk/m_axis_aclk/s_axis_aclk/dclk clock frequency

supported is 250 MHz for the XADC primitive, but this might vary depending on the device

and speed grade selected.

Resource Utilization

For details about resource utilization, visit Performance and Resource Utilization.

Port Descriptions

Table 2-1 describes the input and output ports provided from the XADC Wizard. Availability

of ports is controlled by user-selected parameters. For example, when Dynamic

Reconfiguration is selected, only ports associated with Dynamic Reconfiguration are

exposed. Any port that is not exposed is tied off or connected to a signal labeled as unused

in the delivered source code.

Table 2-1: XADC I/O Signals

Port Direction Description

DRP Ports

di_in[15:0] Input Input data bus for the dynamic reconfiguration port (DRP).

do_out[15:0] Output Output data bus for the dynamic reconfiguration port.

daddr_in[6:0] Input Address bus for the dynamic reconfiguration port.

den_in Input Enable signal for the dynamic reconfiguration port.

dwe_in Input Write enable for the dynamic reconfiguration port.

dclk_in Input Clock input for the dynamic reconfiguration port.

drdy_out Output Data ready signal for the dynamic reconfiguration port.

Send Feedback

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PG091 October 5, 2016

Chapter 2: Product Specification

Control and Reset Ports

reset_in Input

Reset signal for the XADC control logic and maximum/minimum

registers.

convst_in Input

Convert start input. This input is used to control the sampling instant

on the ADC input and is only used in Event Mode Timing (see

Event-Driven Sampling in the 7 Series FPGAs XADC User Guide (UG480)

[Ref 3].

convstclk_in Input

Convert start input. This input is connected to a global clock input on

the interconnect. Like CONVST, this input is used to control the

sampling instant on the ADC inputs and is only used in Event Mode

Timing.

External Analog Inputs

vp_in

vn_in

Input

One dedicated analog-input pair. The XADC has one pair of dedicated

analog-input pins that provide a differential analog input.

vauxp15[15:0]

vauxn15[15:0]

Inputs

16 auxiliary analog-input pairs. Also, the XADC uses 16 differential

digital-input pairs as low-bandwidth differential analog inputs. These

inputs are configured as analog during FPGA configuration.

Alarm and Status Ports

user_temp_alarm_out Output XADC temperature-sensor alarm output.

vccint_alarm_out Output XADC VCCINT-sensor alarm output.

vccaux_alarm_out Output XADC VCCAUX-sensor alarm output.

ot_out Output Over-Temperature alarm output.

channel_out[4:0] Outputs

Channel selection outputs. The ADC input MUX channel selection for

the current ADC conversion is placed on these outputs at the end of an

ADC conversion.

eoc_out Output

End of Conversion signal. This signal transitions to an active-High at

the end of an ADC conversion when the measurement result is written

to the Status registers. For detailed information, see the XADC Timing

section in the 7 Series FPGAs XADC User Guide (UG480) [Ref 3].

eos_out Output

End of Sequence. This signal transitions to an active-High when the

measurement data from the last channel in the Channel Sequencer is

written to the Status registers. For detailed information, see the XADC

Timing section in the 7 Series FPGAs XADC User Guide (UG480) [Ref 3].

busy_out Output

ADC busy signal. This signal transitions High during an ADC

conversion. This signal transitions High for an extended period during

calibration.

jtaglocked_out Output Used to indicate that drp port has been locked by the JTAG interface.

jtagmodified_out Output Used to indicate that a JTAG write to the drp has occurred

jtagbusy_out Output Used to indicate that a JTAG drp transaction is in progress

vbram_alarm_out Output XADC VBRAM sensor alarm output.

vccpint_alarm_out Output XADC VCCPINT sensor alarm output.

Table 2-1: XADC I/O Signals (Cont’d)

Port Direction Description

Send Feedback

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PG091 October 5, 2016

Chapter 2: Product Specification

vccpaux_alarm_out Output XADC VCCPAUX sensor alarm output.

vccddro_alarm_out Output XADC VCCDDROsensor alarm output.

muxaddr_out[4:0] Output Use in external multiplexer mode to decode external MUX channel.

alarm_out Output Logic OR of alarms. Can be used to flag occurrence of any alarm.

temp_out[11:0]

Output

12-bit temperature output bus for the Memory Interface Generator

(MIG). This should be connected to xadc_device_temp_i_pin of MIG.

AXI4-Lite Ports

s_axi_aclk Input AXI clock connects to DCLK of XADC primitive.

s_axi_aresetn Input AXI Reset, Active-Low

s_axi_awaddr[10:0]

Input

AXI Write address. The write address bus gives the address of the write

transaction.

s_axi_awvalid

Input

Write address valid. This signal indicates that a valid write address and

control information are available.

s_axi_awready

Output

Write address ready. This signal indicates that the slave is ready to

accept an address and associated control signals.

s_axi_wdata[31:0] Input Write data

s_axi_wstb[3:0]

Input

Write strobes. This signal indicates which byte lanes to update in

memory.

s_axi_wvalid

Input

Write valid. This signal indicates that valid write data and strobes are

available.

s_axi_wready

Output

Write ready. This signal indicates that the slave can accept the write

data.

s_axi_bresp[1:0]

Output

Write response. This signal indicates the status of the write transaction

00 = OKAY (normal response)

10 = SLVERR (error condition)

11 = DECERR (not issued by core)

s_axi_bvalid

Output

Write response valid. This signal indicates that a valid write response is

available.

s_axi_bready

Input

Response ready. This signal indicates that the master can accept the

response information.

s_axi_araddr[10:0]

Input

Read address. The read address bus gives the address of a read

transaction.

s_axi_arvalid

Input

Read address valid. This signal indicates, when High, that the read

address and control information is valid and remains stable until the

address acknowledgement signal, s_axi_arready, is High.

s_axi_arready

Output

Read address ready. This signal indicates that the slave is ready to

accept an address and associated control signals.

s_axi_rdata[31:0] Output Read data

Table 2-1: XADC I/O Signals (Cont’d)

Port Direction Description

Send Feedback

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