IEEE 1588V2：2008年精密时钟同步协议标准详解

IEEE1588

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IEEE 1588 V2, 全称为“精确时钟同步协议 (Precision Time Protocol) 版本 2”，是IEEE于2008年发布的标准，旨在为网络化的测量和控制系统提供高精度的时间同步解决方案，以替代其2002年的前身IEEE 1588。该标准由IEEE Instrumentation and Measurement Society的Sensor Technology Technical Committee (TC-9) 主导制定，并得到IEEE-SA Standards Board的批准。 IEEE 1588 V2的核心目标是在网络环境中确保时钟间的准确同步，这对于工业自动化、电力系统控制、通信网络以及科学研究等领域中的时间关键应用至关重要。它采用了一种层次化的时间同步模型，包括主时钟（Grand Master, GM）、普通时钟（Transparent Clock, TC）和边缘时钟（Boundary Clock, BC），每个角色都根据自身的功能和角色特点执行特定的同步任务。在协议结构上，IEEE 1588 V2定义了两个主要的同步模式：基本（BPD）和透明（TPD）。基本模式适用于简单的网络环境，而透明模式允许时钟在网络路径上传播且维持精确同步，常用于复杂网络架构。此外，该标准还提供了时间戳的传输机制，允许发送方验证接收方的时间响应，从而确保数据包的可靠交换。该标准引入了几个关键的同步性能指标，如时间同步精度（通常优于1微秒）、同步延迟（即从发送到接收到精确时间戳的时间）和频率稳定性。为了实现这些性能，IEEE 1588 V2采用了差分编码、时间戳对齐和时间戳整形等技术。在部署过程中，IEEE 1588 V2支持多种网络基础设施，包括以太网、光纤通道和无线通信，适应不同应用场景的需求。同时，它也考虑了网络安全问题，如认证和加密，以保护时间和数据的安全性。 IEEE 1588 V2标准对于现代工业控制和通信网络中的时间同步至关重要，它通过严谨的设计和广泛的适用性，极大地提高了时间关键应用的可靠性，为实现高度精确的时间同步奠定了坚实的基础。随着技术的发展，该标准也在不断演进和完善，以应对日益复杂的网络环境和更高的性能需求。

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Table 105 ⎯Translation of flagField from version 2 to version 1 ...................................................... 181

Table 106 ⎯Version 2 fields with no version 1 counterpart............................................................... 182

Table 107 ⎯Version 1 fields with no version 2 counterpart............................................................... 183

Table 108 ⎯Name correspondence..................................................................................................... 183

Table 109 ⎯Mixed system restrictions............................................................................................... 184

Table B.1⎯Relationships between timescales........................................................................................... 199

Table C.1⎯Interpretation of Figure C.1 key values .................................................................................. 202

Table C.2⎯Interpretation of Figure C.2 key values .................................................................................. 203

Table C.3⎯Interpretation of Figure C.3 key values .................................................................................. 205

Table C.4⎯Interpretation of Figure C.4 key values .................................................................................. 207

Table C.5⎯Interpretation of Figure C.5 key values .................................................................................. 209

Table C.6—Interpretation of Figure C.6 key values .................................................................................. 210

Table C.7—Interpretation of Figure C.7 key values .................................................................................. 211

Table C.8—Interpretation of Figure C.8 key values .................................................................................. 213

Table C.9—Interpretation of Figure C.9 key values .................................................................................. 215

Table C.10—Interpretation of Figure C.10 key values............................................................................... 217

Table C.11—Interpretation of Figure C.11 key values............................................................................... 218

Table D.1⎯IPv4 multicast addresses......................................................................................................... 219

Table D.2⎯transportSpecific field values ................................................................................................. 220

Table E.1⎯IPv6 multicast addresses ......................................................................................................... 222

Table F.1⎯Multicast MAC addresses ....................................................................................................... 223

Table F.2⎯Ethernet transport specific field............................................................................................... 224

Table G.1⎯DeviceNet clockIdentity octets 0 through 7............................................................................ 226

Table G.2⎯DeviceNet headers for all PTP message packets .................................................................... 226

Table H.1⎯ControlNet clockIdentity octets 2 through 7........................................................................... 228

Table I.1⎯Mapping of messages............................................................................................................... 231

Table I.2⎯IEEE 802.3 DLPDU syntax ..................................................................................................... 232

Table I.3⎯Multicast MAC address............................................................................................................ 233

Table I.4⎯LT (Length/Type)..................................................................................................................... 234

Table I.6⎯Mapping of the parameter and attribute names ........................................................................ 235

Table I.7⎯Translation of flagField from PTP version 2 to PROFINET.................................................... 236

Table K.1⎯flagField.SECURE flag .......................................................................................................... 242

Table K.2⎯AUTHENTICATION TLV .................................................................................................... 260

Table K.3⎯algorithmId values .................................................................................................................. 261

Table K.4⎯ICV and pad length................................................................................................................. 261

Table K.5⎯AUTHENTICATION_CHALLENGE TLV .......................................................................... 262

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xvi

FIGURES

Figure 1 ⎯Mealy state transition diagram .............................................................................................. 10

Figure 2 ⎯Model of an ordinary clock ................................................................................................... 19

Figure 3 ⎯Model of a boundary clock.................................................................................................... 21

Figure 4 ⎯Model of an end-to-end transparent clock ............................................................................. 22

Figure 5 ⎯End-to-end residence time correction model......................................................................... 23

Figure 6 ⎯Combined ordinary and end-to-end transparent clock........................................................... 25

Figure 7 ⎯Model of a peer-to-peer transparent clock............................................................................. 27

Figure 8 ⎯Peer-to-peer residence time and link delay correction model................................................ 28

Figure 9 ⎯Combined ordinary and peer-to-peer transparent clock. ....................................................... 30

Figure 10 ⎯Simple master−slave clock hierarchy ............................................................................... 32

Figure 11 ⎯Pruned mesh topology ...................................................................................................... 33

Figure 12 ⎯Basic synchronization message exchange ........................................................................ 34

Figure 13 ⎯Link delay measurement................................................................................................... 35

Figure 14 ⎯Timestamp generation model............................................................................................ 36

Figure 15 ⎯Hierarchical topology ....................................................................................................... 37

Figure 16 ⎯Linear topology................................................................................................................. 38

Figure 17 ⎯Multiply connected topology............................................................................................ 39

Figure 18 ⎯Bridging disparate technologies........................................................................................ 40

Figure 19 ⎯Definition of latency constants ......................................................................................... 45

Figure 20 ⎯Propagation asymmetry .................................................................................................... 47

Figure 21 ⎯Port model ........................................................................................................................ 48

Figure 22 ⎯Scaled log variance hysteresis .......................................................................................... 60

Figure 23 ⎯State machine for a full implementation........................................................................... 78

Figure 24 ⎯State machine for a slave-only implementation................................................................ 79

Figure 25 ⎯STATE_DECISION_EVENT logic ................................................................................. 81

Figure 26 ⎯State decision algorithm ................................................................................................... 87

Figure 27 ⎯Data set comparison algorithm, part 1 .............................................................................. 89

Figure 28 ⎯Data set comparison algorithm, part 2 .............................................................................. 90

Figure 29 ⎯Receipt of Announce message logic................................................................................. 96

Figure 30 ⎯Receipt of Sync message logic ......................................................................................... 98

Figure 31 ⎯Receipt of Follow_Up message logic ............................................................................. 100

Figure 32 ⎯Receipt of Delay_Req message logic ............................................................................. 101

Figure 33 ⎯Receipt of Delay_Resp message logic............................................................................ 103

Figure 34 ⎯Delay request-response path length measurement.......................................................... 110

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xvii

Figure 35 ⎯Peer delay link measurement .......................................................................................... 113

Figure 36 ⎯Permitted mixed system configuration ........................................................................... 183

Figure 37 ⎯Profile print form............................................................................................................ 186

Figure C.1⎯Master, end-to-end, and slave one-step clocks; no asymmetry correction ............................ 201

Figure C.2⎯Master, end-to-end, and slave one-step clocks; with asymmetry correction ......................... 202

Figure C.3⎯Master two-step and end-to-end transparent and slave one-step clocks; with asymmetry

correction.................................................................................................................................................... 204

Figure C.4⎯Master and end-to-end transparent, two-step, and one-step, slave clocks; with asymmetry

correction.................................................................................................................................................... 206

Figure C.5⎯One-step master, two-step end-to-end transparent, and one-step slave clocks; with asymmetry

correction.................................................................................................................................................... 208

Figure C.6—One-step peer responder, end-to-end transparent, and peer requestor clocks; with asymmetry

correction.................................................................................................................................................... 210

Figure C.7—One-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks;

with asymmetry correction ......................................................................................................................... 211

Figure C.8—Two-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks:

option 1; with asymmetry correction.......................................................................................................... 212

Figure C.9—Two-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks:

option 2; with asymmetry correction.......................................................................................................... 214

Figure C.10—Two-step peer responder, one-step end-to-end transparent, and one-step peer requestor

clocks: option 2; with asymmetry correction.............................................................................................. 216

Figure C.11—One-step peer master, two-step peer-to-peer transparent, and one-step peer slave clocks; time

computation................................................................................................................................................ 217

Figure G.1⎯ Event message timestamp point ........................................................................................... 225

Figure I.1⎯PROFINET region combined with domains........................................................................... 231

Figure K.1⎯PTP secure message processing ............................................................................................ 252

Figure K.2⎯Challenge processing............................................................................................................. 254

Figure K.3⎯Secure transmit processing.................................................................................................... 256

Figure K.4⎯Secure event processing ........................................................................................................ 258

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