A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA18HTPLL
+NB_HTPVDD
+AVDD2
NB_THERMAL_DC
NB_THERMAL_DA
TV_LUMA
NB_RESET#
+AVDD1
RED
BLUE
CRT_VSYNC
GREEN
CRT_HSYNC
NB_PWRGD
NB_ALLOW_LDTSTOP
NB_LDTSTOP#
+VDDLT18
TV_COMPS
TV_CRMA
+AVDDQ
+VDDLTP18
RED
GREEN
BLUE
+NB_PLLVDD
+VDDA18PCIEPLL
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
NB_PWM
ENBKL
UMA_CRT_CLK16
UMA_CRT_DAT16
HDMIDAT_UMA18
NB_PWRGD20
CRT_HSYNC14,16
CRT_VSYNC14,16
UMA_ENVDD 17
INV_PWM 17,33
NBGFX_CLK15
NBGFX_CLK#15
CLK_SBLINK_BCLK15
CLK_SBLINK_BCLK#15
HPD 18
CLK_NBHT15
CLK_NBHT#15
PLT_RST#14,19,25,26,27,32,33
RED16
GREEN16
BLUE16
AUX_CAL14
RS780_DFT_GPIO_014
SUS_STAT# 20
LVDS_A2+ 17
LVDS_A0+ 17
LVDS_A1+ 17
LVDS_ACLK- 17
HDMICLK_UMA18
LVDS_ACLK+ 17
LVDS_A2- 17
LVDS_A0- 17
LVDS_A1- 17
LCD_DDC_DAT17
LCD_DDC_CLK17
NB_OSC_14.318M15
LDT_STOP#6,19
CPU_LDT_REQ#6,19
SUS_STAT_R# 14
ENBKL 33
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.1VS
+1.1VS
+1.8VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4111P
0.4
RS780 VEDIO/CLK GEN
Custom
11 54Friday, March 07, 2008
2007/08/02 2008/08/02
Compal Electronics, Inc.
Strap pin
AVDD=100mA
Strap pin
PA_RS780A4
placement close to NB ball
NB temp to SB
Strap pin
L
0.08A/10mil/1vias
02/18 Change R371 from 10K to 300 ohm.
02/22 Reserve R62, R63, R64.
03/03 Add C1120.
03/06 Add R1085 and R1086.
03/03 Add Change backlight enable to LVDS_ENA_BL.
03/03 Add D58 and connect to PWM
R62 150_0402_1%@
1 2
R71
4.7K_0402_5%
1 2
C179
2.2U_0603_6.3V4Z
1
2
L4
0_0603_5%
C180
2.2U_0603_6.3V4Z
1
2
L5
BLM18PG121SN1D_0603
1 2
C1120
0.1U_0402_16V4Z
1
2
L2
BLM18PG121SN1D_0603
1 2
R67
0_0402_5%
1 2
L7
BLM18PG121SN1D_0603
1 2
R1085 0_0402_5%
1 2
R88 10K_0402_5%
12
R69 0_0402_5%
1 2
L10
BLM18PG121SN1D_0603
1 2
T49PAD
R73
0_0402_5%
@
1 2
C175
2.2U_0603_6.3V4Z
1
2
T50PAD
C172
2.2U_0603_6.3V4Z
1
2
T47 PAD
R63 150_0402_1%@
1 2
R1084
0_0402_5%
@
1 2
C176
2.2U_0603_6.3V4Z
1
2
C173
0.1U_0402_16V4Z
1
2
L9
BLM18PG121SN1D_0603
1 2
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780MN_FCBGA528
VDDA18HTPLL
H17
SYSRESETb
D8
POWERGOOD
A10
LDTSTOPb
C10
ALLOW_LDTSTOP
C12
REFCLK_P/OSCIN(OSCIN)
E11
PLLVDD(NC)
A12
HPD(NC)
D10
DDC_CLK0/AUX0P(NC)
A8
DDC_DATA0/AUX0N(NC)
B8
THERMALDIODE_P
AE8
THERMALDIODE_N
AD8
I2C_CLK
B9
STRP_DATA
B10
GFX_REFCLKP
T2
GFX_REFCLKN
T1
GPP_REFCLKP
U1
GPP_REFCLKN
U2
PLLVDD18(NC)
D14
PLLVSS(NC)
B12
TXOUT_L0P(NC)
A22
TXOUT_L0N(NC)
B22
TXOUT_L1P(NC)
A21
TXOUT_L1N(NC)
B21
TXOUT_L2P(NC)
B20
TXOUT_L2N(DBG_GPIO0)
A20
TXOUT_L3P(NC)
A19
TXOUT_U0P(NC)
B18
TXOUT_L3N(DBG_GPIO2)
B19
TXOUT_U0N(NC)
A18
TXOUT_U1P(PCIE_RESET_GPIO3)
A17
TXOUT_U1N(PCIE_RESET_GPIO2)
B17
TXOUT_U2P(NC)
D20
TXOUT_U2N(NC)
D21
TXOUT_U3P(PCIE_RESET_GPIO5)
D18
TXOUT_U3N(NC)
D19
TXCLK_LP(DBG_GPIO1)
B16
TXCLK_LN(DBG_GPIO3)
A16
TXCLK_UP(PCIE_RESET_GPIO4)
D16
TXCLK_UN(PCIE_RESET_GPIO1)
D17
VDDLTP18(NC)
A13
VSSLTP18(NC)
B13
C_Pr(DFT_GPIO5)
E17
Y(DFT_GPIO2)
F17
COMP_Pb(DFT_GPIO4)
F15
RED(DFT_GPIO0)
G18
TMDS_HPD(NC)
D9
I2C_DATA
A9
TESTMODE
D13
HT_REFCLKN
C24
HT_REFCLKP
C25
SUS_STAT#(PWM_GPIO5)
D12
GREEN(DFT_GPIO1)
E18
BLUE(DFT_GPIO3)
E19
DAC_VSYNC(PWM_GPIO6)
B11
DAC_HSYNC(PWM_GPIO4)
A11
DAC_RSET(PWM_GPIO1)
G14
AVDD1(NC)
F12
AVDD2(NC)
E12
REDb(NC)
G17
GREENb(NC)
F18
AVDDDI(NC)
F14
AVSSDI(NC)
G15
AVDDQ(NC)
H15
AVSSQ(NC)
H14
VDDLT18_2(NC)
B15
VDDLT33_1(NC)
A14
VDDLT33_2(NC)
B14
VSSLT1(VSS)
C14
VSSLT2(VSS)
D15
VDDLT18_1(NC)
A15
VSSLT3(VSS)
C16
VSSLT4(VSS)
C18
VSSLT5(VSS)
C20
LVDS_DIGON(PCE_TCALRP)
E9
LVDS_BLON(PCE_RCALRP)
F7
LVDS_ENA_BL(PWM_GPIO2)
G12
VSSLT6(VSS)
E20
VDDA18PCIEPLL1
D7
VDDA18PCIEPLL2
E7
BLUEb(NC)
F19
AUX_CAL(NC)
C8
GPPSB_REFCLKP(SB_REFCLKP)
V4
GPPSB_REFCLKN(SB_REFCLKN)
V3
DDC_DATA1/AUX1N(NC)
A7
DDC_CLK1/AUX1P(NC)
B7
DAC_SCL(PCE_RCALRN)
F8
DAC_SDA(PCE_TCALRN)
E8
REFCLK_N(PWM_GPIO3)
F11
VSSLT7(VSS)
C22
RSVD
G11
R68
0_0402_5%
1 2
R64 150_0402_1%@
1 2
T46 PAD
L6
BLM18PG121SN1D_0603
1 2
L11
BLM18PG121SN1D_0603
1 2
R72
4.7K_0402_5%
1 2
C171
2.2U_0603_6.3V4Z
1
2
C178
2.2U_0603_6.3V4Z
1
2
R1086 100K_0402_5%
1 2
R80
1.8K_0402_5%
1 2
C174
4.7U_0805_10V4Z
1
2
C170
2.2U_0603_6.3V4Z
1
2
T48 PAD
R371 300_0402_5%
1 2
R65 715_0402_1%
1 2
R1072 100K_0402_5%@
1 2
R66 0_0402_5%
1 2
R77 0_0402_5%
1 2
L3
BLM18PG121SN1D_0603
1 2