TCA6416A：低电压16位I2C/SMBus接口扩展器特性

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TCA6416A是一款由TI公司生产的低电压16位I2C和SMBus I/O扩展器，它集成了中断输出、复位功能以及配置寄存器，专为需要在不同电压等级（1.8V, 2.5V, 3.3V, 或5VPP）下进行数据传输和信号扩展的应用设计。该器件具有以下关键特性： 1. **电源范围**：TCA6416A支持宽广的电源供电，可以从1.65V到5.5V工作，这使得它能够适应多种系统电压需求，同时保持兼容性和稳定性。 2. **低电压I/O端口**：它拥有5个电压容忍I/O端口，可以在1.65V至5.5V的电源电压范围内工作，允许与多种外部设备通信，包括1.8V SCL和SDA信号线，支持400kHz的快速I2C通信速率。 3. **中断功能**：TCA6416A集成了一个可编程的主动低电平中断输出（INT），用户可以通过该引脚实现对系统事件的检测和处理，增强了系统的实时响应能力。 4. **复位输入**：它具有一个活跃低的复位输入（RESET），允许通过外部信号控制设备的初始化过程，有助于系统的可靠启动和恢复。 5. **配置灵活性**：内部配置寄存器提供了对I/O端口极性反转和工作模式的设置选项，允许用户根据具体应用调整接口的特性。 6. **封装类型**：TCA6416A提供三种封装形式，包括ZQSPACKAGE、RTWPACKAGE和PWPACKAGE，每种封装都有不同的引脚布局，但都包含GND、VCCP、SDA、SCL、ADDR等核心信号以及可能的备用接地或电气隔离中心垫。 7. **中心垫处理**：如果使用中心垫，必须作为次要地连接，或者确保其电气上保持开路，以避免意外短路或干扰。 TCA6416A是一款高度灵活且功能强大的I/O扩展器，适用于需要在低电压环境下实现高速I2C通信，并具备中断和配置能力的嵌入式系统设计。其广泛的电源兼容性、丰富的接口选项以及中断管理能力，使其成为现代电子设计中的理想选择。

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SDA

SCL

S P

StartCondition

StopCondition

SDA

SCL

DataLine

Change

1 2 8 9

NACK

ACK

DataOutput

byTransmitter

DataOutput

byReceiver

SCL From

Master

Start

Condition

ClockPulsefor

Acknowledgment

TCA6416A

SCPS194 – MAY 2009 .......................................................................................................................................................................................................

www.ti.com

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1 ).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3 ). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 1. Definition of Start and Stop Conditions

Figure 2. Bit Transfer

Figure 3. Acknowledgment on the I

C Bus

Product Folder Link(s): TCA6416A

Device Address

Slave Address

0 0

R/W

Fixed

Programmable

Control Register and Command Byte

B2 B1

B0B5

TCA6416A

www.ti.com

....................................................................................................................................................................................................... SCPS194 – MAY 2009

Interface Definition

BIT

BYTE

7 (MSB) 6 5 4 3 2 1 0 (LSB)

C slave address L H L L L L ADDR R/ W

P07 P06 P05 P04 P03 P02 P01 P00

I/O data bus

P17 P16 P15 P14 P13 P12 P11 P10

The address of the TCA6416A is shown in Figure 4 .

Figure 4. TCA6416A Address

Address Reference

ADDR I

C BUS SLAVE ADDRESS

L 64 (decimal), 40 (hexadecimal)

H 66 (decimal), 42 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is

stored in the control register in the TCA6416A. Three bits of this data byte state the operation (read or write) and

the internal registers (input, output, polarity inversion, or configuration) that will be affected. This register can be

written or read through the I

C bus. The command byte is sent only during a write transmission.

Once a new command has been sent, the register that was addressed continues to be accessed by reads until a

new command byte has been sent.

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND BYTE POWER-UP

(HEX) DEFAULT

B7 B6 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 00 Input Port 0 Read byte xxxx xxxx

(1)

0 0 0 0 0 0 0 1 01 Input Port 1 Read byte xxxx xxxx

0 0 0 0 0 0 1 0 02 Output Port 0 Read/write byte 1111 1111

0 0 0 0 0 0 1 1 03 Output Port 1 Read/write byte 1111 1111

0 0 0 0 0 1 0 0 04 Polarity Inversion Port 0 Read/write byte 0000 0000

0 0 0 0 0 1 0 1 05 Polarity Inversion Port 1 Read/write byte 0000 0000

0 0 0 0 0 1 1 0 06 Configuration Port 0 Read/write byte 1111 1111

0 0 0 0 0 1 1 1 07 Configuration Port 1 Read/write byte 1111 1111

(1) Undefined

Product Folder Link(s): TCA6416A

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