多核系统并行故障仿真提升性能

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本文主要探讨了多核系统中的高性能并行故障仿真技术。随着信息技术的快速发展，传统的单核处理器已经无法满足现代计算密集型应用的需求，因此多核系统逐渐成为主流。多核系统通过在单个芯片上集成多个处理核心，能够实现并发执行，从而显著提高计算效率，特别是对于那些涉及大量数据处理和复杂模拟任务，如故障仿真，其性能提升尤为关键。故障仿真是一个耗时的过程，它需要对硬件结构有深入理解并定制特殊的算法和方法来优化。为了加速这个过程，论文提出了一种基于多线程的并行故障仿真策略，旨在充分利用多核平台的并发特性。该方法的核心在于将硬件的不同部分同时利用，通过独立分配每个核心处理不同的门级输入值，实现了对故障模型的并行执行。这种方法旨在打破传统单线程仿真中的瓶颈，提高整体的吞吐量和资源利用率。在设计上，作者强调了软件与硬件平台的紧密配合，因为有效的并行化并非仅仅增加核心数量就能自动实现，而是需要精细的软件调整以适应多核架构的特点。这可能涉及到线程同步、数据共享策略、负载均衡以及错误处理等问题，以确保各核心之间的协同工作无缝进行。为了实现这一目标，论文可能会探讨以下关键技术点： 1. **并行任务划分**：将故障仿真任务分解成可分割的工作单元，以便多个核心可以同时处理。 2. **线程调度和通信**：如何有效地在多个核心之间分发和协调工作，减少同步开销。 3. **内存管理**：处理并行执行中的数据一致性问题，可能采用共享内存或分布式内存模型。 4. **性能分析与优化**：通过基准测试和性能监控，持续优化算法以适应硬件的实时变化。 5. **错误检测和恢复**：在并行环境中，如何处理可能出现的硬件或软件错误，保证结果的正确性。本文旨在通过创新的并行故障仿真技术，为多核系统提供一种有效的方法，以提高其在故障模拟领域的性能，这对于设计和验证复杂的电子系统具有重要意义。研究者们通过对软件与硬件的深度集成，期待能够大幅缩短故障模拟的时间，降低开发成本，并为未来高性能计算领域的发展打开新的可能性。

High-Performance Parallel Fault Simulation for

Multi-Core Systems

Masoomeh Karami

∗

, Mohammad-hashem Haghbayan

∗

, Masoumeh Ebrahimi

†

, Hamid Nejatollahi

‡

Hannu Tenhunen

†

, and Juha Plosila

∗

Department of Future Technologies, University of Turku, Turku, Finland.

†

Department of Electronics and Embedded Systems, Royal Institute of Technology (KTH), Kista, Sweden.

‡

University of California, Irvine, CA USA.

Emails:

∗

{mkaram, mohhag, juplos}@utu.ﬁ

†

{mebr,hannu}@kth.se

‡

hnejatol@uci.edu

Abstract—Fault simulation is a time-consuming process that

requires customized methods and techniques to accelerate it.

Multi-threading and Multi-core approaches are two promising

techniques that can be exploited to accelerate the fault simulation

process by using different parts of the hardware at the same

time. However, an efﬁcient parallelization is obtained only by the

reﬁnement of software with respect to the hardware platform. In

this paper, a parallel multi-thread fault simulation technique is

proposed to accelerate the simulation process on multi-core plat-

forms. In this approach, the gate input values are independently

assigned to each thread. Each input value carries the information

of several parallel simulation processes. This provides a multi-

thread parallel fault simulation environment. The experimental

results show that the proposed technique can efﬁciently use

the hardware platform. In a single-core platform, the proposed

technique can reduce the time by 25% while in a dual-core

increasing the thread approximately halves the execution time.

Index Terms—Multi-core system, multi-threading, paralleliza-

tion, fault simulation

I. INTRODUCTION

Fault simulation (FS) plays an essential role in different

ﬁelds, such as test pattern generation, built-in-self-test, con-

trollability, and observability analysis [1], [2]. This process is

a challenging and time-consuming task in the VLSI design.

In FS, a circuit-under-test (CUT) is simulated for a given

fault model and a set of test patterns. This process is often

computationally intensive, particularly for modern systems that

require a large number of test patterns.

One of the most popular fault models for VLSI circuits is

the stuck-at fault model [2]. Several works have used parallel

and concurrent FS approaches to minimize the FS execution

time for the stuck-at fault model in single-core [2], [3] and

multi-core processors [4], [5]. They also use different methods

such as mixed-level fault simulation, parallelization, and event-

driven to accelerate the FS process. Mixed-level FS is an ap-

proach where non-faulty parts of a circuit are simulated faster

using a higher abstraction level, e.g., behavioral level [6]. As

FS has parallelizable characteristics, parallel processing has

been widely used for minimizing the execution time. One

parallelization technique is to partition the circuit into mutually

exclusive parts and simulate them in parallel [7], [8]. Other

parallelization solutions are based on simulating the circuit

in parallel for different sets of faults (data-parallel) or test

patterns (pattern-parallel) [9], [10].

There are two methods for implementing gate-level fault

simulation: time-driven FS and event-driven FS. In the time-

driven FS, the simulator calculates and updates all the gates’

input/output variables in each small time epoch. In the event-

driven FS, the gates’ input/output variables are calculated

based on the new occurred event, e.g., a change in the wire

value. The event-driven method is more efﬁcient compared to

the time-driven method by being faster, using less memory,

and being more ﬂexible [11], [12].

In this paper, a parallel event-driven FS technique is pro-

posed for multi-core systems to minimize the FS time. We

describe the entire process from fault injection to scheduling

tasks for parallel computing on different cores. The proposed

technique is based on parallel processing of the occurred

events in each level of the netlist.

II. PARALLEL EVENT-DRIVEN FAULT SIMULATION

In this section, we investigate two separate techniques to

reduce the fault-simulation (FS) time, i.e., parallel FS [4],

[5] and event-driven FS [13], [14], [11]. The considered fault

model in this paper is stuck-at-0 (S@0) or stuck-at-1 (S@1)

[2]. In a simple FS technique, after generating faults and

eliminating the overlapping faults, i.e., fault collapsing [2],

[15], faults are injected into the design. Then, the output of

the design is compared with the expected value, i.e., golden

output. If the output is the same as the golden output, it means

the fault is not propagated to the output, and thus it is masked.

Otherwise, it is said that the injected fault is observed and

detected. For example, Figure 1 shows a 1-bit multiplexer

where the output should be 0 when the signals {A, B, and

SELECT } are {000}. However, the S@1 fault on wire 3

results in OUT =1, which is different from the golden result,

and thus a fault is detected.

Fig. 1: An example of stuck-at FS in a 1-bit multiplier

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