HSAIL语言规范V1.1：虚拟ISA与编程模型详解

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HSA Programmers Reference Manual V1.1 是一份针对Heterogeneous System Architecture (HSA) 的重要文档，它详述了Heterogeneous System Architecture Intermediate Language (HSAIL)。HSAIL是一个虚拟机器和中间语言，专为HSA架构设计者提供规范。这个版本的文档日期为2016年2月2日，版权归属于HSA基金会，所有权利保留。 HSAIL是HSA架构编程模型的核心部分，它定义了如何在不同类型的处理器（如CPU、GPU和加速器）上编写和执行统一的代码。手册涵盖了以下几个关键方面： 1. **虚拟ISA和编程模型**：HSAIL提供了一种抽象的编程接口，使得开发者无需关心底层硬件的具体实现细节，可以编写可跨平台运行的程序。它强调了异构系统中的并行计算和数据移动策略，促进了高性能计算的标准化。 2. **编译器设计**：手册为HSAIL编译器的开发者提供了指导，包括从高级语言源代码到HSAIL指令集的转换过程，以及如何优化代码以适应不同硬件特性。 3. **对象格式（BRIG）**：BRIG (Binary Representation for Intermediate Grid) 是HSAIL编译后的机器码格式，它紧凑且易于处理，便于在目标设备上执行。 4. **版权和许可**：手册的内容受到严格的版权保护，未经HSA基金会明确书面许可，不得复制、分发或以任何形式利用。然而，开发者可以在不修改或删除任何商标、版权声明或其他通知的情况下，使用此规格来实现其中的功能。 5. **HSA基金会成员**：HSA基金会的创始人、推广者、支持者、贡献者、学术会员或附属成员有权使用这份文档，但并不意味着他们获得了生产、披露或分销文档内容或基于其制造、使用或销售相关产品的权利。 HSA Programmers Reference Manual V1.1 是开发人员、工具制造商和研究人员的重要参考，它提供了构建、优化和部署跨平台异构系统应用的必要知识和标准。理解和遵循这份手册对于推动HSA生态系统的成长至关重要。

Contents

Figure 4–84 integerArrayTypedConstant Syntax Diagram 96

Figure 4–85 halfArrayTypedConstant Syntax Diagram 97

Figure 4–86 singleArrayTypedConstant Syntax Diagram 97

Figure 4–87 doubleArrayTypedConstant Syntax Diagram 97

Figure 4–88 packedArrayTypedConstant Syntax Diagram 98

Figure 4–89 imageArrayTypedConstant Syntax Diagram 98

Figure 4–90 samplerArrayTypedConstant Syntax Diagram 98

Figure 4–91 signalArrayTypedConstant Syntax Diagram 98

Figure 4–92 aggregateConstant Syntax Diagram 99

Figure 4–93 aggregateConstantItem Syntax Diagram 99

Figure 4–94 aggregateConstantAlign Syntax Diagram 99

Figure 4–95 aggregateConstantZero Syntax Diagram 100

Figure 4–96 optInitializer Syntax Diagram 102

Figure 4–97 packedTypedConstant Syntax Diagram 111

Figure 5–1 Example of Broadcast 148

Figure 5–2 Example of Rotate 148

Figure 5–3 Example of Unpack 149

Figure 6–1 Memory Hierarchy 178

Figure 13–1 extension Syntax Diagram 289

Figure 13–2 location Syntax Diagram 292

Figure 13–3 pad Syntax Diagram 293

Figure 13–4 pragma Syntax Diagram 293

Figure 13–5 pragmaOperand Syntax Diagram 294

Figure 14–1 moduleHeader Syntax Diagram 302

Tables

Table 2–1 Wavefront 0 Through 6 29

Table 2–2 Memory Segment Access Rules 36

Table 2–3 Machine Model Data Sizes 40

Table 4–1 Text Constants and Results of the Conversion 100

Table 4–2 Base Data Types 107

Table 4–3 Packed Data Types and Possible Lengths 108

Table 4–4 Opaque Data Types 109

Table 4–5 Packing Controls for Instructions With One Source Input 110

Table 4–6 Packing Controls for Instructions With Two Source Inputs 110

Table 5–1 Syntax for Integer Arithmetic Instructions 127

Table 5–2 Syntax for Packed Versions of Integer Arithmetic Instructions 127

Table 5–3 Syntax for Integer Optimization Instruction 131

Table 5–4 Syntax for 24-Bit Integer Optimization Instructions 132

Table 5–5 Syntax for Integer Shift Instructions 133

Table 5–6 Syntax for Individual Bit Instructions 135

Table 5–7 Inputs and Results for popcount Instruction 136

Table 5–8 Syntax for Bit String Instructions 137

Table 5–9 Inputs and Results for firstbit and lastbit Instructions 140

Table 5–10 Syntax for Copy (Move) Instructions 141

Table 5–11 Syntax for Shuffle and Interleave Instructions 143

Table 5–12 Syntax for Pack and Unpack Instructions 144

Table 5–13 Bit Selectors for shuffle instruction 146

Table 5–14 Syntax for Bit Conditional Move (cmov) Instruction 150

Table 5–15 Syntax for Floating-Point Arithmetic Instructions 151

Table 5–16 Syntax for Packed Versions of Floating-Point Arithmetic Instructions 151

Table 5–17 Syntax for Floating-Point Optimization Instruction 154

Table 5–18 Syntax for Floating-Point Bit Instructions 156

Table 5–19 Class Instruction Source Operand Condition Bits 156

16 | HSAProgrammer's Reference Manual, Version 1.1 Draft

HSAProgrammer's Reference Manual, Version 1.1 Draft | 17

Table 5–20 Syntax for Packed Versions of Floating-Point Bit Instructions 157

Table 5–21 Syntax for Native Floating-Point Instructions 158

Table 5–22 Syntax for Multimedia Instructions 160

Table 5–23 Syntax for Segment Checking (segmentp) Instruction 163

Table 5–24 Syntax for Segment Conversion Instructions 164

Table 5–25 Syntax for Compare (cmp) Instruction 166

Table 5–26 Syntax for Packed Version of Compare (cmp) Instruction 166

Table 5–27 Floating-Point Comparisons 168

Table 5–28 Conversion Methods 170

Table 5–29 Notation for Conversion Methods 171

Table 5–30 Syntax for Conversion (cvt) Instruction 171

Table 5–31 Rules for Rounding for Conversions 172

Table 5–32 Integer Rounding Modes 174

Table 6–1 Syntax for Load (ld) Instruction 184

Table 6–2 Syntax for Store (st) Instruction 188

Table 6–3 Syntax for Atomic Instructions 192

Table 6–4 Syntax for Atomic No Return Instructions 196

Table 6–5 Syntax for Signal Instructions 199

Table 6–6 Syntax for memfence Instruction 203

Table 7–1 Image Geometry Properties 206

Table 7–2 Channel Order Properties 209

Table 7–3 Channel Type Properties 211

Table 7–4 Channel Order, Channel Type, and Image Geometry Combination 216

Table 7–5 Image Handle Properties 225

Table 7–6 Image Instruction Combinations 229

Table 7–7 Syntax for Read Image Instruction 233

Table 7–8 Syntax for Load Image Instruction 234

Table 7–9 Syntax for Store Image Instruction 236

Table 7–10 Syntax for Query Image and Query Sampler Instructions 237

Table 7–11 Explanation of imageProperty modifier 238

Table 7–12 Explanation of samplerProperty modifier 238

Table 7–13 Syntax for imagefence Instruction 239

Table 8–1 Syntax for Branch Instructions 241

Table 9–1 Syntax for Barrier Instructions 243

Table 9–2 Syntax for fbar Instructions 245

Table 9–3 Syntax for Cross-Lane Instructions 255

Table 10–1 Syntax for direct call Instruction 264

Table 10–2 Syntax for switch call Instruction 265

Table 10–3 Syntax for indirect call Instruction 267

Table 10–4 Syntax for ret Instruction 269

Table 10–5 Syntax for Allocate Memory (alloca) Instruction 269

Table 11–1 Syntax for Kernel Dispatch Packet Instructions 271

Table 11–2 Syntax for Exception Instructions 274

Table 11–3 Syntax for Exception Instructions 276

Table 11–4 Syntax for Miscellaneous Instructions 279

Table 13–1 Control Directives for Low-Level Performance Tuning 295

Table 18–1 Formats of Directives in the hsa_code Section 341

Table 18–2 Formats of Instructions in the hsa_code Section 350

Table 18–3 Formats of Operands in the hsa_operand Section 361

Table 18–4 BRIG Syntax for Integer Arithmetic Instructions 371

Table 18–5 BRIG Syntax for Integer Optimization Instruction 372

Table 18–6 BRIG Syntax for 24-Bit Integer Optimization Instructions 372

Table 18–7 BRIG Syntax for Integer Optimization Instructions 373

Table 18–8 BRIG Syntax for Individual Bit Instructions 373

Table 18–9 BRIG Syntax for Bit String Instructions 373

Contents

Chapter 1. Overview 1.1 What Is HSAIL?

CHAPTER 1.

Overview

This chapter provides an overview of Heterogeneous System Architecture Intermediate Language (HSAIL).

1.1 What Is HSAIL?

The Heterogeneous System Architecture (HSA) is designed to efficiently support a wide assortment of data-

parallel and task-parallel programming models. A single HSA system can support multiple instruction sets

based on CPU(s), GPU(s), and specialized processor(s).

HSA supports two machine models: large mode (64-bit address space) and small mode (32-bit address

space).

Programmers normally build code for HSA in a virtual machine and intermediate language called HSAIL

(Heterogeneous System Architecture Intermediate Language). Using HSAIL allows a single program to

execute on a wide range of platforms, because the native instruction set has been abstracted away.

HSAIL is required for parallel computing on an HSA platform.

This manual describes the HSAIL virtual machine and the HSAIL intermediate language.

An HSA implementation consists of:

l Hardware components that execute one or more machine instruction set architectures (ISAs).

Supporting multiple ISAs is a key component of HSA.

l An HSA runtime that is a library of services that supports the execution of HSAIL programs including

a finalizer and a loader:

A finalizer translates HSAIL code into the appropriate machine code if the hardware

components cannot support HSAIL natively.

A loader loads machine code onto hardware components.

Each implementation is able to execute the same HSAIL virtual machine and language, though different

implementations might run at different speeds.

A device that participates in the HSA memory model is called an agent.

An HSAIL virtual machine consists of multiple agents including at least one host CPU and one kernel agent:

l A host CPU is an agent that also supports the native CPU instruction set and runs the host operating

system and the HSA runtime. As an agent, the host CPU can dispatch commands to a kernel agent

using memory instructions to construct and enqueue Architected Queuing Language (AQL) packets on

User Mode Queues associated with the kernel agent. In some systems, a host CPU can also act as a

kernel agent (with appropriate HSAIL finalizer and AQL mechanisms).

l A kernel agent is an agent that supports the HSAIL instruction set and includes a packet processor

that supports the AQL packet format including the kernel dispatch packet. As an agent, a kernel

agent can dispatch commands to any kernel agent (including itself) using memory instructions to

construct and enqueue AQL packets on User Mode Queues associated with the kernel agent.

20 | HSAProgrammer's Reference Manual, Version 1.1 Draft

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