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Samsung S3C6410X RISC Microprocessor User's Manual
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"三星S3C6410X用户手册,这是一份关于ARM11架构的S3C6410X RISC微处理器的详细参考文档,由三星电子于2008年发布,修订版1.10。文档包含有关该处理器的重要通知、准确性和专利权信息,并提醒用户三星有权在不通知的情况下随时改进产品或规格。"
三星S3C6410X是一款基于ARM11内核的RISC(精简指令集计算)微处理器,设计用于高效能的应用场景。RISC架构以其简洁的指令集和优化的处理能力而闻名,常用于嵌入式系统和移动设备。S3C6410X是三星电子在2008年推出的一款产品,可能被广泛应用于智能手机、平板电脑、工业控制设备等。
该用户手册详细介绍了S3C6410X处理器的特性和功能,包括但不限于:
1. 内核架构:ARM11是ARM公司的一个32位微处理器系列,S3C6410X可能具备高性能、低功耗的设计,以及多种流水线和缓存机制。
2. 性能指标:可能涵盖了时钟速度、内存接口、I/O接口、功耗管理等方面的数据。
3. 硬件集成:可能内置了各种外设控制器,如USB、以太网、LCD控制器、音频接口等,便于系统集成。
4. 片上系统(SoC)特性:S3C6410X作为一个SoC,可能集成了电源管理单元、安全模块、存储器控制器等组件。
5. 开发支持:手册可能提供了SDK、开发工具链、调试接口等开发人员所需的信息。
6. 系统级设计指南:如何将S3C6410X与外围硬件和软件结合,构建完整的应用系统。
文档中还强调了重要通知,指出三星对出版物中的可能错误或遗漏不承担责任,且不对使用该信息可能导致的后果负责。此外,三星保留随时更改产品或规格的权利,但并不强制更新文档以反映这些变更。购买S3C6410X半导体器件的用户不会因购买获得三星或任何其他公司的专利使用权。三星明确声明其产品不提供任何特定用途的适用性保证,也不承担任何与产品应用或使用相关的责任。
由于提供的部分内容有限,无法提供更深入的技术细节,但可以推断出S3C6410X用户手册将是一个全面的资源,对于开发者和工程师来说,它是理解和利用该处理器的关键参考资料。
xvi S3C6410X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 14 Display Controller
14.4.5 Palette usage .................................................................................................................................14-16
14.4.5.1 Palette Configuration and Format Control..............................................................................14-16
14.4.6 Window Blending ...........................................................................................................................14-18
14.4.6.1 Overview.................................................................................................................................14-18
14.4.6.2 Blending Diagram/Details ...........................................................................................................14-20
14.4.7 COLOR-KEY Function...................................................................................................................14-22
14.4.8 VTIME CONTROLLER OPERATION ............................................................................................14-25
14.4.8.1 RGB Interface.........................................................................................................................14-25
14.4.8.2 I80 Interface Controller..........................................................................................................14-26
14.4.9 LDI Command Control ...................................................................................................................14-27
14.4.9.1 Auto Command.......................................................................................................................14-27
14.4.9.2 Normal Command ..................................................................................................................14-27
14.4.10 I80 CPU Interface Trigger............................................................................................................14-29
14.4.11 Interrupt........................................................................................................................................14-29
14.4.12 Virtual Display ..............................................................................................................................14-29
14.4.13 RGB Interface IO .........................................................................................................................14-31
14.4.14 LCD I80 INTERFACE IO..............................................................................................................14-32
14.4.14 ITU-R BT.601 INTERFACE IO.....................................................................................................14-33
14.4.15 LCD DaTA PiN MAP....................................................................................................................14-34
14.4.16 LCD NORMAL/BY-PASS MODE SELECTION ...........................................................................14-36
14.5 Programmer’s Model.............................................................................................................................14-37
14.5.1 Overview ........................................................................................................................................14-37
14.5.2 SFR Memory Map..........................................................................................................................14-37
14.6 Individual Register Descriptions............................................................................................................14-40
14.6.1 Video Main Control 0 Register.......................................................................................................14-40
14.6.2 Video Main Control 1 Register.......................................................................................................14-42
14.6.3 Video Main Control 2 Register.......................................................................................................14-43
14.6.4 VIDEO Time Control 0 Register.....................................................................................................14-43
14.6.5 Video Time Control 1 Register.......................................................................................................14-44
14.6.6 VIDEO Time Control 2 Register.....................................................................................................14-44
14.6.7 Window 0 Control Register ............................................................................................................14-44
14.6.8 Window 1 Control Register ...........................................................................................................14-46
14.6.9 Window 2 Control Register ............................................................................................................14-48
14.6.10 Window 3 Control Register ..........................................................................................................14-50
14.6.11 Window 4 Control Register ..........................................................................................................14-51
14.6.12 Window 0 Position Control A Register.........................................................................................14-52
14.6.13 Window 0 Position Control B Register.........................................................................................14-52
14.6.14 Window 0 Position Control C Register.........................................................................................14-52
14.6.15 Window 1 Position Control A Register.........................................................................................14-53
14.6.16 Window 1 Position Control B Register.........................................................................................14-53
14.6.17 Window 1 Position Control C Register..................................................................................
......14-54
14.6.18 Window 1 Position Control D Register.........................................................................................14-54
14.6.19 Window 2 Position Control A Register.........................................................................................14-54
S3C6410X_USER’S MANUAL_REV 1.10 xvii
Table of Contents (Continued)
Chapter 14 Display Controller
14.6.20 Window 2 Position Control B Register ........................................................................................14-55
14.6.21 Window 2 Position Control C Register ........................................................................................14-55
14.6.22 Window 2 Position Control D Register ........................................................................................14-55
14.6.23 Window 3 Position Control A Register ........................................................................................14-56
14.6.24 Window 3 Position Control B Register ........................................................................................14-56
14.6.25 Window 3 Position Control C Register ........................................................................................14-57
14.6.26 Window 4 Position Control a Register.........................................................................................14-57
14.6.27 Window 4 Position Control B Register ........................................................................................14-58
14.6.28 Window 4 Position Control C Register ........................................................................................14-58
14.6.29 FRAME Buffer Address 0 Register..............................................................................................14-59
14.6.30 FRAME Buffer Address 1 Register..............................................................................................14-59
14.6.31 FRAME Buffer Address 2 Register..............................................................................................14-60
14.6.32 VIDEO interrupt Control 0 Register .............................................................................................14-60
14.6.33 VIDEO interrupt Control 1 Register .............................................................................................14-61
14.6.34 Win1 Color Key 0 Register ..........................................................................................................14-62
14.6.35 WIN 1 Color key 1 Register.........................................................................................................14-62
14.6.36 Win2 Color Key 0 Register ..........................................................................................................14-63
14.6.37 WIN2 Color key 1 Register..........................................................................................................14-63
14.6.38 Win3 Color Key 0 Register ..............................................................................................
............14-64
14.6.39 WIN3 Color key 1 Register..........................................................................................................14-64
14.6.40 Win4 Color Key 0 Register ..........................................................................................................14-65
14.6.41 WIN4 Color key 1 Register..........................................................................................................14-66
14.6.42 Dithering Control 1 Register ........................................................................................................14-67
14.6.43 WIN0 Color MAP .........................................................................................................................14-67
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.45 WIN2 Color MAP .........................................................................................................................14-68
14.6.46 WIN3 Color MAP .........................................................................................................................14-68
14.6.47 WIN4 Color MAP .........................................................................................................................14-69
14.6.48 Window Palette control Register .................................................................................................14-69
14.6.49 I80 / RGB Trigger Control Register .............................................................................................14-70
14.6.50 ITU 601 Interface control 0..........................................................................................................14-70
14.6.51 LCD I80 Interface Control 0.........................................................................................................14-71
14.6.52 LCD I80 Interface Control 1.........................................................................................................14-72
14.6.53 LCD I80 Interface Command Control 0.......................................................................................14-72
14.6.54 LCD I80 Interface Command Control 1.......................................................................................14-74
14.6.55 I80 System Interface Manual Command Control 0 .....................................................................14-74
14.6.56 I80 System Interface Manual Command Control 1 .....................................................................14-75
14.6.57 I80 System Interface Manual Command Control 2 .....................................................................14-75
14.6.58 LCD I80 Interface Command.......................................................................................................14-76
14.6.59 Window 2’s Palette Data .............................................................................................................14-76
14.6.60 Window 3’s Palette Data .............................................................................................................14-77
14.6.61 Window 4’s Palette Data .............................................................................................................14-77
14.6.62 WIN0 Palette Ram Access Address (not SFR) ...........................................................................14-77
14.6.63 WIN1 Palette Ram Access Address (not SFR) ...........................................................................14-78
xviii S3C6410X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 15 Post Processor
15.1 Overview................................................................................................................................................15-1
15.2 Features ................................................................................................................................................15-2
15.3 A Source and Destination Image Data Format .....................................................................................15-3
15.3.1 DMA Mode Operation ....................................................................................................................15-4
15.3.2 FIFO Mode Operation....................................................................................................................15-7
15.4 Image Size and Scale Ratio..................................................................................................................15-7
15.5 DMA operation of Source and Destination Image.................................................................................15-9
15.5.1 Start address..................................................................................................................................15-10
15.5.2 End address...................................................................................................................................15-10
15.6 Frame Management of POST Processor..............................................................................................15-12
15.6.1 Per Frame Management Mode......................................................................................................15-12
15.6.2 Free Run Mode ..............................................................................................................................15-12
15.7 Register File Lists..................................................................................................................................15-13
15.7.1 MODE Control Register .................................................................................................................15-15
15.7.3 Pre-Scale Image Size Register......................................................................................................15-17
15.7.4 Source Image Size Register ..........................................................................................................15-18
15.7.5 Horizontal Main Scale Ratio Register ............................................................................................15-18
15.7.6 Vertical Main Scale Ratio Register ................................................................................................15-18
15.7.7 Destination Image Size Register ...................................................................................................15-19
15.7.8 Pre-Scale Shift Factor Register .....................................................................................................15-19
15.7.9 DMA Start Address Register..............................................................................................
............20
15.7.10 DMA End Address Register.........................................................................................................15-21
15.7.11 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register .............................................15-22
15.7.12 Next Frame DMA Start Address Register....................................................................................15-23
15.7.13 Next Frame DMA End Address Register.....................................................................................15-24
15.7.14 DMA Start address Register for Output Cb and Cr .....................................................................15-24
15.7.15 DMA End Address Register for Output Cb and Cr ......................................................................15-25
15.7.16 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr ..........15-25
15.7.17 15.26 Next Frame DMA Start Address Register for Output Cb and Cr.......................................15-25
15.7.18 Next Frame DMA End Address Register for Output Cb and Cr ..................................................15-26
15.7.19 POSTENVID Register to Enable Video Processing ....................................................................15-26
15.7.20 MODE Control Register 2 ............................................................................................................15-27
S3C6410X_USER’S MANUAL_REV 1.10 xix
Table of Contents (Continued)
Chapter 16 TV Scaler
16.1 Overview ...............................................................................................................................................16-1
16.2 Features................................................................................................................................................16-2
16.3 A Source and Destination Image Data Format.....................................................................................16-3
16.3.1 DMA Mode Operation....................................................................................................................16-4
16.3.2 FIFO Mode Operation....................................................................................................................16-7
16.4 Image Size and Scale Ratio..................................................................................................................16-7
16.5 DMA operation of Source and Destination Image ................................................................................16-9
16.5.1 Start address .................................................................................................................................16-10
16.5.2 End address...................................................................................................................................16-10
16.6 Frame Management of TV Scaler.........................................................................................................16-12
16.6.1 Per Frame Management Mode......................................................................................................16-12
16.6.2 Free Run Mode..............................................................................................................................16-12
16.7 Register File Lists .................................................................................................................................16-13
16.7.1 MODE Control Register.................................................................................................................16-15
16.7.3 Pre-Scale Image Size Register .....................................................................................................16-17
16.7.4 Source Image Size Register..........................................................................................................16-18
16.7.5 Horizontal Main Scale Ratio Register............................................................................................16-18
16.7.6 Vertical Main Scale Ratio Register................................................................................................16-18
16.7.7 Destination Image Size Register ...................................................................................................16-19
16.7.8 Pre-Scale Shift Factor Register.....................................................................................................16-19
16.7.9 DMA Start Address Register .........................................................................................................16-20
16.7.10 DMA End Address Register.........................................................................................................16-20
16.7.11 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register...........................................16-21
16.7.12 Next Frame DMA Start Address Register ...................................................................................16-21
16.7.13 Next Frame DMA End Address Register.....................................................................................16-22
16.7.14 DMA Start Address Register for Output Cb and Cr.....................................................................16-22
16.7.15 DMA End Address Register for Output Cb and Cr......................................................................16-23
16.7.16 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register for Output Cb and Cr ........16-23
16.7.17 Next Frame DMA Start Address Register for Output Cb and Cr.................................................16-23
16.7.18 Next Frame DMA End Address Register for Output Cb and Cr..................................................16-24
16.7.19 POSTENVID Register for Enable Video Processing...................................................................16-24
16.7.20 MODE Control Register 2............................................................................................................16-25
xx S3C6410X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 17 TV Encoder
17.1 Overview................................................................................................................................................17-1
17.2 Feature ..................................................................................................................................................17-1
17.3 Block Diagram .......................................................................................................................................17-2
17.4 Functional Descriptions.........................................................................................................................17-3
17.4.1 Composition Of Analog Composite Signal.....................................................................................17-4
17.4.2 Common Ntsc System ...................................................................................................................17-5
17.4.3 Common Pal System .....................................................................................................................17-6
17.4.4 Composition Of Screen..................................................................................................................17-7
17.4.5 Requested Horizontal Timing ........................................................................................................17-8
17.4.6 Requested Vertical Timing.............................................................................................................17-9
17.4.7 Macrovision (Anti Taping) ..............................................................................................................17-10
17.5 Dac Board Configure Guide ..................................................................................................................17-11
17.6 Tv Encoder Register Summary .............................................................................................................17-12
17.7 Individual Register Descriptions............................................................................................................17-13
17.7.1 TVENCREG1 .................................................................................................................................17-13
17.7.2 TVENCREG2 .................................................................................................................................17-14
17.7.3 TVENCREG3 .................................................................................................................................17-14
17.7.4 TVENCREG4 .................................................................................................................................17-14
17.7.5 TVENCREG5 .................................................................................................................................17-15
17.7.6 TVENCREG6 .................................................................................................................................17-15
17.7.7 TVENCREG7 .................................................................................................................................17-15
17.7.8 TVENCREG8 ...............................................................................................................
..................17-16
17.7.9 TVENCREG9 .................................................................................................................................17-16
17.7.10 TVENCREG10 .............................................................................................................................17-17
17.7.11 TVENCREG11 .............................................................................................................................17-17
17.7.12 TVENCREG12 .............................................................................................................................17-17
17.7.13 TVENCREG14 .............................................................................................................................17-18
17.7.14 TVENCREG15 .............................................................................................................................17-18
17.7.15 TVENCREG18 .............................................................................................................................17-20
17.7.16 TVENCREG19 .............................................................................................................................17-20
17.7.17 TVENCREG20 .............................................................................................................................17-21
17.7.18 TVENCREG21 .............................................................................................................................17-22
17.7.19 TVENCREG23 .............................................................................................................................17-22
17.7.20 TVENCREG25 .............................................................................................................................17-23
17.7.21 TVENCREG26 .............................................................................................................................17-24
17.7.22 TVENCREG27 .............................................................................................................................17-24
17.7.23 TVENCREG28 .............................................................................................................................17-25
17.7.24 TVENCREG29 .............................................................................................................................17-25
17.7.25 TVENCREG30 .............................................................................................................................17-25
17.7.26 TVENCREG31 .............................................................................................................................17-26
17.7.27 TVENCREG32 .............................................................................................................................17-26
17.7.28 TVENCREG33 .............................................................................................................................17-26
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