瑞萨RH850/F1M汽车电子用户手册 Rev.1.03 May 2016

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"瑞萨Renesas RH850/F1M用户手册 (R01UH0518EJ0103) Rev.1.03 May 2016" 这篇用户手册详细介绍了瑞萨电子的32位单片机RH850/F1M，该芯片特别适用于汽车电子领域，如车身控制模块(BCM)。手册涵盖了硬件方面的信息，是瑞萨RH850家族的一部分，旨在帮助用户理解和应用这款高性能微控制器。瑞萨RH850/F1M是一款专为汽车电子系统设计的微控制器，具有高效能、高可靠性以及对汽车环境的适应性。其特性可能包括但不限于以下几点： 1. **高性能内核**：RH850/F1M可能内置了一个或多个高性能的32位CPU核心，能够处理复杂的计算任务，满足汽车电子系统对于实时性和处理能力的需求。 2. **嵌入式存储器**：通常包含闪存（用于程序存储）和SRAM（用于数据处理和临时存储），提供足够的存储空间以满足不同应用的需求。 3. **外围接口**：RH850/F1M可能集成了多种接口，如CAN（控制器局域网络）、LIN（局部互联网络）、UART（通用异步收发传输器）等，便于与汽车内部的各种传感器和执行器通信。 4. **电源管理**：为了满足汽车环境中多变的电压和电流条件，该芯片可能包含先进的电源管理和节能特性，确保在各种工作条件下稳定运行。 5. **安全特性**：考虑到汽车电子系统的安全性至关重要，RH850/F1M可能包含了故障检测、错误纠正代码（ECC）和安全启动等功能，以增强系统的可靠性和安全性。 6. **开发工具支持**：瑞萨通常会提供相应的开发工具链，包括编译器、调试器和模拟器，以简化开发流程并加速产品上市时间。手册中的警告和注意事项提醒用户，文档中提供的电路、软件和相关信息仅供参考，用户在实际设计时应自行负责。瑞萨电子虽然在准备这些信息时已尽合理谨慎，但不承担因使用这些信息导致的任何损失的责任。 RH850/F1M用户手册为工程师提供了全面的技术指南，包括芯片的功能描述、应用示例、配置方法和故障排除步骤，以帮助他们成功地将该微控制器集成到汽车电子产品中。通过深入阅读和理解手册，开发者可以充分发挥RH850/F1M的优势，设计出高效、可靠的汽车电子解决方案。

10.1 Overview..................................................................................................................................... 416

10.1.1 Functional Overview ......................................................................................................... 416

10.1.2 Power-On Clear (POC)..................................................................................................... 416

10.1.3 Low Voltage Indicator Circuit (LVI) ................................................................................... 416

10.1.3.1 LVI Reference Voltage .......................................................................................... 416

10.1.3.2 LVI Reset (LVIRES) .............................................................................................. 417

10.1.3.3 LVI Interrupt (INTLVIL / INTLVIH) ......................................................................... 417

10.1.3.4 LVI Setting Procedure ........................................................................................... 418

10.1.3.5 Clock Supply to the LVI......................................................................................... 418

10.1.4 Core Voltage Monitor (CVM) ............................................................................................ 419

10.1.4.1 CVM Reset (CVMRES

) ......................................................................................... 419

10.1.4.2 CVM Setting .......................................................................................................... 419

10.1.4.3 Diagnostic (DIAG) Mode ....................................................................................... 419

10.1.4.4 Clock Supply to the CVM ...................................................................................... 420

10.1.5 RAM Retention Voltage Indicator (Very-Low-Voltage Detection Circuit:VLVI) ................. 421

10.1.5.1 Clock Supply to the VLVI....................................................................................... 421

10.1.5.2 Retention RAM Content Retention ........................................................................ 421

10.1.6 Block Diagram .................................................................................................................. 422

10.2 Registers..................................................................................................................................... 423

10.2.1 List of Registers................................................................................................................ 423

10.2.2 Low-Voltage Indicator Reset Control Registers................................................................ 424

10.2.2.1 LVICNT — LVI Control Register............................................................................ 424

10.2.3 Core Voltage Monitor Control Registers........................................................................... 425

10.2.3.1 CVMF — CVM Factor Register ............................................................................. 425

10.2.3.2 CVMDE — CVM Detection Enable Register ......................................................... 426

10.2.3.3 CVMDIAG — CVM Diagnostic Mode Setting Register.......................................... 427

10.2.4 Very-Low-Voltage Detection Control Registers ................................................................ 428

10.2.4.1 VLVF — Very-Low-Voltage Detection Register..................................................... 428

10.2.4.2 VLVFC — Very-Low-Voltage Detection Clear Register ........................................ 429

Section 11 Clock Controller ........................................................................................... 430

11.1 Features of Clock Controller of RH850/F1M............................................................................... 430

11.2 Configuration of Clock Controller................................................................................................ 432

11.2.1 Clock Generation Circuits................................................................................................. 434

11.2.2 Clock Selection................................................................................................................. 435

11.2.3 Clock Domains ................................................................................................................. 436

11.2.4 Resetting Clock Oscillators............................................................................................... 436

11.3 Clock Oscillators ......................................................................................................................... 437

11.3.1 Main Oscillator (MainOSC)............................................................................................... 437

11.3.2 Sub Oscillator (SubOSC).................................................................................................. 439

11.3.3 High Speed Internal Oscillator (HS IntOSC)..................................................................... 440

11.3.4 Low Speed Internal Oscillator (LS IntOSC) ...................................................................... 441

11.3.5 PLL0/PLL1........................................................................................................................ 442

11.3.5.1 PLL0 Parameters .................................................................................................. 444

11.3.5.2 PLL1 Parameters .................................................................................................. 446

11.4 Registers..................................................................................................................................... 447

11.4.1 List of Registers................................................................................................................ 447

11.4.2 Clock Oscillator Registers ................................................................................................ 449

11.4.2.1 MOSCE — MainOSC Enable Register ................................................................. 449

11.4.2.2 MOSCS — MainOSC Status Register .................................................................. 450

11.4.2.3 MOSCC — MainOSC Control Register................................................................. 451

11.4.2.4 MOSCST — MainOSC Stabilization Time Register .............................................. 452

11.4.2.5 MOSCSTPM — MainOSC Stop Mask Register .................................................... 453

11.4.2.6 SOSCE — SubOSC Enable Register ................................................................... 454

11.4.2.7 SOSCS — SubOSC Status Register .................................................................... 455

11.4.2.8 SOSCST — SubOSC Stabilization Time Register ................................................ 456

11.4.2.9 ROSCE — HS IntOSC Enable Register................................................................ 457

11.4.2.10 ROSCS — HS IntOSC Status Register................................................................. 458

11.4.2.11 ROSCSTPM — HS IntOSC Stop Mask Register .................................................. 459

11.4.2.12 PLL0E — PLL0 Enable Register ........................................................................... 460

11.4.2.13 PLL0S — PLL0 Status Register ............................................................................ 461

11.4.2.14 PLL0C — PLL0 Control Register .......................................................................... 462

11.4.2.15 PLL0ST — PLL0 Stabilization Time Register........................................................ 474

11.4.2.16 PLL1E — PLL1 Enable Register ........................................................................... 475

11.4.2.17 PLL1S — PLL1 Status Register ............................................................................ 476

11.4.2.18 PLL1C — PLL1 Control Register .......................................................................... 477

11.4.3 Clock Selector Control Register ....................................................................................... 488

11.4.3.1 WDTA0 Clock Domain C_AWO_WDTA................................................................ 488

11.4.3.2 TAUJ Clock Domain C_AWO_TAUJ..................................................................... 491

11.4.3.3 RTCA Clock Domain C_AWO_RTCA ................................................................... 496

11.4.3.4 ADCA0 Clock Domain C_AWO_ADCA................................................................. 501

11.4.3.5 FOUT Clock Domain C_AWO_FOUT ................................................................... 506

11.4.3.6 CPU Clock Domain C_ISO_CPUCLK ................................................................... 509

11.4.3.7 Peripheral Clock Domains C_ISO_PERI1 and C_ISO_PERI2 ............................. 513

11.4.3.8 RLIN Clock Domains C_ISO_LIN.......................................................................... 517

11.4.3.9 ADCA1 Clock Domain C_ISO_ADCA ................................................................... 522

11.4.3.10 RS-CAN Clock Domains C_ISO_CAN and C_ISO_CANOSC.............................. 526

11.4.3.11 CSI Clock Domain C_ISO_CSI ............................................................................. 532

11.4.3.12 IIC Clock Domain C_ISO_IIC ................................................................................ 534

11.5 Clock Domain Setting Method .................................................................................................... 536

11.5.1 Clock Domain Setting ....................................................................................................... 536

11.5.1.1 Overview of Clock Selector Register..................................................................... 536

11.5.1.2 Setting Procedure for Clock Domain .................................................................... 537

11.5.2 Stopping the Clock in Stand-By Mode.............................................................................. 537

11.5.3 Clock Domain Settings ..................................................................................................... 538

11.6 Frequency Output Function (FOUT) ........................................................................................... 540

11.6.1 Functional Overview ......................................................................................................... 540

11.6.2 Registers .......................................................................................................................... 541

11.6.2.1 List of Registers..................................................................................................... 541

11.6.2.2 Clock Supply ......................................................................................................... 541

11.6.2.3 FOUTDIV — Clock Division Ratio Register........................................................... 542

11.6.2.4 FOUTSTAT — Clock Divider Status Register ....................................................... 543

11.7 Clock Monitor A (CLMA) ............................................................................................................. 544

11.7.1 Features of RH850/F1M CLMA ........................................................................................ 544

11.7.1.1 Number of Channels ............................................................................................. 544

11.7.1.2 Register Base Addresses...................................................................................... 544

11.7.1.3 Clock Supply ......................................................................................................... 544

11.7.1.4 Reset Sources....................................................................................................... 545

11.7.1.5 Internal Input/Output Signals................................................................................. 545

11.7.2 Overview........................................................................................................................... 545

11.7.2.1 Functional Overview.............................................................................................. 545

11.7.3 Enabling CLMA................................................................................................................. 547

11.7.4 Functions .......................................................................................................................... 547

11.7.4.1 Detection of Abnormal Clock Frequencies ............................................................ 547

11.7.4.2 Notification of Abnormal Clock Frequency ............................................................ 549

11.7.5 Registers .......................................................................................................................... 550

11.7.5.1 List of Registers..................................................................................................... 550

11.7.5.2 CLMAnCTL0 — CLMAn Control Register 0 .......................................................... 551

11.7.5.3 CLMAnCMPH — CLMAn Compare Register H .................................................... 552

11.7.5.4 CLMAnCMPL — CLMAn Compare Register L...................................................... 553

11.7.5.5 CLMATEST — CLMA Test Register ..................................................................... 554

11.7.5.6 CLMATESTS — CLMA Test Status Register........................................................ 555

11.7.5.7 CLMAnEMU0 — CLMAn Emulation Register 0 .................................................... 556

11.7.6 Usage Notes for CLMAn................................................................................................... 557

Section 12 Stand-By Controller (STBC)......................................................................... 558

12.1 Functions .................................................................................................................................... 558

12.1.1 Types of Stand-By Mode .................................................................................................. 558

12.1.2 Wake-Up Control .............................................................................................................. 559

12.1.2.1 Wake-Up Factors for Stand-By Modes.................................................................. 559

12.1.2.2 Setting of Wake-Up Factors .................................................................................. 561

12.1.3 On-Chip Debug Wake-Up................................................................................................. 563

12.1.4 I/O Buffer Control.............................................................................................................. 564

12.1.4.1 I/O Buffer Hold State ............................................................................................ 564

12.1.4.2 I/O Buffers during STOP Mode ............................................................................. 564

12.1.4.3 I/O Buffers during DeepSTOP Mode..................................................................... 564

12.1.5 Transition to Stand-By Mode ............................................................................................ 565

12.1.6 Clock Supply..................................................................................................................... 565

12.2 Registers..................................................................................................................................... 566

12.2.1 List of Registers................................................................................................................ 566

12.2.2 Details of Stand-By Controller Control Registers ............................................................. 567

12.2.2.1 STBC0PSC — Power Save Control Register ....................................................... 567

12.2.2.2 STBC0STPT — Power Stop Trigger Register....................................................... 568

12.2.2.3 WUF0/WUF20/WUF_ISO0 — Wake-Up Factor Registers.................................... 569

12.2.2.4 WUFMSK0/WUFMSK20/WUFMSK_ISO0 — Wake-Up Factor Mask Registers... 570

12.2.2.5 WUFC0/WUFC20/WUFC_ISO0 — Wake-Up Factor Clear Registers .................. 571

12.2.2.6 IOHOLD — I/O Buffer Hold Control Register ........................................................ 572

12.3 Mode Transition .......................................................................................................................... 573

12.3.1 STOP Mode...................................................................................................................... 573

12.3.2 DeepSTOP Mode ............................................................................................................. 575

12.3.3 Cyclic RUN Mode ............................................................................................................. 578

12.3.4 Cyclic STOP Mode ........................................................................................................... 580

12.4 Writing to the Stand-By Controller Related Registers................................................................. 581

12.5 Cautions when Using Stand-By Modes ...................................................................................... 581

12.5.1 Cautions Concerning Transitioning to DeepSTOP Mode When Using a Debugger......... 581

Section 13 Low-Power Sampler (LPS) .......................................................................... 582

13.1 Features of RH850/F1M LPS ..................................................................................................... 582

13.1.1 Number of Units ............................................................................................................... 582

13.1.2 Register Base Address..................................................................................................... 583

13.1.3 Clock Supply..................................................................................................................... 583

13.1.4 Interrupt Request.............................................................................................................. 583

13.1.5 Reset Sources .................................................................................................................. 584

13.1.6 External Input/Output Signals........................................................................................... 584

13.1.7 Internal Input/Output Signals ............................................................................................ 584

13.2 Overview..................................................................................................................................... 585

13.2.1 Functional Overview ......................................................................................................... 585

13.3 Registers..................................................................................................................................... 586

13.3.1 List of Registers................................................................................................................ 586

13.3.2 SCTLR — LPS Control Register ...................................................................................... 587

13.3.3 EVFR — Event Flag Register........................................................................................... 589

13.3.4 DPSELR0 — DPIN Select Register 0............................................................................... 590

13.3.5 DPSELRM — DPIN Select Register M............................................................................. 591

13.3.6 DPSELRH — DPIN Select Register H ............................................................................. 592

13.3.7 DPDSR0 — DPIN Data Set Register 0 ............................................................................ 593

13.3.8 DPDSRM — DPIN Data Set Register M .......................................................................... 594

13.3.9 DPDSRH — DPIN Data Set Register H ........................................................................... 595

13.3.10 DPDIMR0 — DPIN Data Input Monitor Register 0 ........................................................... 596

13.3.11 DPDIMR1 — DPIN Data Input Monitor Register 1 ........................................................... 596

13.3.12 DPDIMR2 — DPIN Data Input Monitor Register 2 ........................................................... 597

13.3.13 DPDIMR3 — DPIN Data Input Monitor Register 3 ........................................................... 597

13.3.14 DPDIMR4 — DPIN Data Input Monitor Register 4 ........................................................... 598

13.3.15 DPDIMR5 — DPIN Data Input Monitor Register 5 ........................................................... 598

13.3.16 DPDIMR6 — DPIN Data Input Monitor Register 6 ........................................................... 599

13.3.17 DPDIMR7 — DPIN Data Input Monitor Register 7 ........................................................... 599

13.3.18 CNTVAL — Count Value Register.................................................................................... 600

13.3.19 SOSTR — LPS Operation Status Register ...................................................................... 601

13.4 Digital Input Mode....................................................................................................................... 602

13.5 Analog Input Mode...................................................................................................................... 607

Section 14 External Memory Access Controller (MEMC) .............................................. 611

14.1 Features of MEMC...................................................................................................................... 611

14.1.1 Products that Incorporate MEMC ..................................................................................... 611

14.1.2 Register Base Address..................................................................................................... 611

14.1.3 Clock Supply..................................................................................................................... 612

14.1.4 Reset Sources .................................................................................................................. 612

14.1.5 External Input/Output Signals........................................................................................... 612

14.2 Overview..................................................................................................................................... 613

14.2.1 Functional Overview ......................................................................................................... 613

14.2.1.1 Multiplexed Bus ..................................................................................................... 613

14.2.1.2 Chip Select Output Function ................................................................................. 613

14.2.1.3 Data Endian Setting Function................................................................................ 613

14.2.1.4 Programmable Wait Setting Functions.................................................................. 613

14.2.1.5 External Wait Function .......................................................................................... 614

14.2.1.6 External Wait Error Detection Function ................................................................. 614

14.3 Registers..................................................................................................................................... 615

14.3.1 List of Registers................................................................................................................ 615

14.3.2 DEC — Data Endian Configuration Register.................................................................... 616

14.3.3 DWC — Data Wait Configuration Register....................................................................... 617

14.3.4 DHC — Data Hold Wait Configuration Register ............................................................... 618

14.3.5 DSC — Data Setup Wait Configuration Register ............................................................. 619

14.3.6 AWC — Address Wait Configuration Register ................................................................. 620

14.3.7 ICC — Idle Cycle Configuration Register ......................................................................... 621

14.3.8 EWC — External Wait Error Configuration Register ........................................................ 622

14.4 Functions .................................................................................................................................... 623

14.4.1 Bus Control Functions ...................................................................................................... 623

14.4.1.1 Chip Select Output Function ................................................................................. 623

14.4.1.2 Bus Sizing Function............................................................................................... 625

14.4.1.3 Data Endian Setting Function................................................................................ 625

14.4.2 Wait Functions.................................................................................................................. 626

14.4.2.1 Programmable Data Wait Function ....................................................................... 627

14.4.2.2 External Wait Function .......................................................................................... 628

14.4.2.3 External Wait Error Detection Function ................................................................. 629

14.4.2.4 Data Setup Wait Function ..................................................................................... 630

14.4.2.5 Data Hold Wait Function ....................................................................................... 631

14.4.2.6 Address Setup Wait Function................................................................................ 632

14.4.2.7 Address Hold Wait Function.................................................................................. 633

14.4.2.8 Idle Insertion Function ........................................................................................... 634

14.4.3 Memory Connection Example .......................................................................................... 635

14.4.3.1 SRAM Connection Example.................................................................................. 635

14.4.4 Data Access Flow............................................................................................................. 636

14.4.4.1 Data Flow for Byte Access (for Reading and Writing) ........................................... 637

14.4.4.2 Data Flow for Half-Word Read Access.................................................................. 639

14.4.4.3 Data Flow for Half-Word Write Access.................................................................. 641

14.4.4.4 Data Flow for Word Read Access ......................................................................... 643

14.4.4.5 Data Flow for Word Write Access ......................................................................... 646

14.5 Notes on Use of MEMC .............................................................................................................. 648

Section 15 Clocked Serial Interface G (CSIG)............................................................... 649

15.1 Features of RH850/F1M CSIG ................................................................................................... 649

15.1.1 Number of Units................................................................................................................ 649

15.1.2 Register Base Address..................................................................................................... 649

15.1.3 Clock Supply..................................................................................................................... 649

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