LPC800 Cortex-M0+微控制器 datasheet:低功耗、USART/I2C接口详解

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"LPC800数据手册（UM10601）是NXP公司发布的一份详细的技术文档，针对的是基于ARM Cortex-M0+架构的LPC800系列微控制器，包括LPC810M021FN8、LPC811M001FDH16、LPC812M101FDH16和LPC812M101FD20/LPC812M101FDH20等型号。该手册主要涵盖了产品的详细规格、功能介绍、接口描述以及低功耗模式和电源管理单元（PMU）的使用指导。在手册的开头，文档声明所有提供的信息都受法律免责声明约束，并强调了版权归属。版本1.2更新于2013年3月14日，这次修订包括了多方面的内容。编辑上的改进使得文档更加清晰易懂，表40“PLL配置示例”被更新，反映了最新的设计优化。表92的“Pattern match bit-slices source register (PMSRC, 地址0xA000402C)”的位描述也得到了修正，这有助于用户理解这些寄存器的功能。章节5“LPC800的减低功耗模式与电源管理单元”经过了扩充，特别添加了对ARM Cortex-M0+核心低功耗模式的详细介绍，这对于电池供电设备的开发者来说是非常重要的部分。同时，关于闪存配置寄存器（FLASHCFG, 地址0x40040010）的描述中，不再依赖于系统频率，提供了更精确的访问时间信息。此外，手册还特别提醒用户注意如何防止内部引脚出现浮动问题，给出了相应的预防措施和操作指南，这对于电路设计和系统稳定性具有实际指导意义。 LPC800数据手册是开发人员进行硬件设计、理解和利用LPC800系列微控制器的必备参考资料，它全面展示了芯片的功能特性，以及如何在实际应用中高效地管理和控制其工作状态。"

User manual Rev. 1.2 — 14 March 2013 16 of 337

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Chapter 4: LPC800 System configuration (SYSCON)

Related registers:

Table 63 “PIO0_8 register (PIO0_8, address 0x4004 4038) bit description”

Table 62 “PIO0_9 register (PIO0_9, address 0x4004 4034) bit description”

Table 106 “Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description”

Table 10 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description”

4.4 Pin description

The SYSCON inputs and outputs are assigned to external pins through the switch matrix.

See Section 9.3.1 “Connect an internal signal to a package pin”

to assign the CLKOUT

function to a pin on the LPC800 package.

See Section 9.3.2

to enable the clock input, the oscillator pins, and the external reset

input.

4.5 General description

4.5.1 Clock generation

The system control block generates all clocks for the chip. Only the low-power oscillator

used for wake-up timing is controlled by the PMU. Except for the USART clock and the

clock to configure the glitch filters of the digital I/O pins, the clocks to the core and

peripherals run at the same frequency. The maximum system clock frequency is 30 MHz.

See Figure 3

Remark: The main clock frequency is limited to 100 MHz.

Table 4. SYSCON pin description

Function Direction Pin Description SWM register Reference

CLKOUT O any CLKOUT clock output. PINASSIGN8 Table 105

CLKIN I PIO0_1/ACMP_I2/CLKIN External clock input to the system

PLL. Disable the ACMP_I2 function

in the PINENABLE register.

PINENABLE0 Table 106

XTALIN I PIO0_8/XTALIN Input to the system oscillator. PINENABLE0 Table 106

XTALOUT O PIO0_9/XTALOUT Output from the system oscillator. PINENABLE0 Table 106

RESET I RESET/PIO0_5 External reset input PINENABLE0 Table 106

User manual Rev. 1.2 — 14 March 2013 18 of 337

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Chapter 4: LPC800 System configuration (SYSCON)

4.5.3 Configuration of reduced power-modes

The system control block configures analog blocks that can remain running in the reduced

power modes (the BOD and the watchdog oscillator for safe operation) and enables

various interrupts to wake up the chip when the internal clocks are shut down in

Deep-sleep and Power-down modes. For details, see the following registers:

Section 4.6.32 “Power configuration register”

Section 4.6.29 “Start logic 1 interrupt wake-up enable register”

4.5.4 Reset and interrupt control

The peripheral reset control register in the system control register allows to assert and

release individual peripheral resets. See Table 7

Up to eight external pin interrupts can be assigned to any digital pin in the system control

block (see Section 4.6.27 “Pin interrupt select registers”

4.6 Register description

All system control block registers reside on word address boundaries. Details of the

registers appear in the description of each function.

Reset values describe the content of the registers after the boot loader has executed.

All address offsets not shown in Table 5

are reserved and should not be written to.

Table 5. Register overview: System configuration (base address 0x4004 8000)

Name Access Offset Description Reset value Reference

SYSMEMREMAP R/W 0x000 System memory remap 0x2 Table 6

PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 1FFF Table 7

SYSPLLCTRL R/W 0x008 System PLL control 0 Table 8

SYSPLLSTAT R 0x00C System PLL status 0 Table 9

- - 0x010 Reserved - -

- - 0x014 Reserved - -

SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 10

WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0A0 Table 11

- - 0x028 Reserved - -

- - 0x02C Reserved - -

SYSRSTSTAT R/W 0x030 System reset status register 0 Table 12

SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0 Table 13

SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0 Table 14

MAINCLKSEL R/W 0x070 Main clock source select 0 Table 15

MAINCLKUEN R/W 0x074 Main clock source update enable 0 Table 16

SYSAHBCLKDIV R/W 0x078 System clock divider 1 Table 17

SYSAHBCLKCTRL R/W 0x080 System clock control 0x1F Tab le 18

UARTCLKDIV R/W 0x094 USART clock divider 0 Table 19

- - 0x098 Reserved - -

User manual Rev. 1.2 — 14 March 2013 19 of 337

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Chapter 4: LPC800 System configuration (SYSCON)

- - 0x09C Reserved - -

- - 0x0A0 -

0x0BC

Reserved - -

- - 0x0CC Reserved - -

CLKOUTSEL R/W 0x0E0 CLKOUT clock source select 0 Table 20

CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0 Table 21

CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0 Table 22

UARTFRGDIV R/W 0x0F0 USART fractional generator divider value 0 Table 23

UARTFRGMULT R/W 0x0F4 USART fractional generator multiplier value 0 Table 24

EXTTRACECMD R/W 0x0FC External trace buffer command register 0 Table 25

PIOPORCAP0 R 0x100 POR captured PIO status 0 user dependent Table 26

- - 0x104 Reserved - -

IOCONCLKDIV6 R/W 0x134 Peripheral clock 6 to the IOCON block for

programmable glitch filter

0x0000 0000 Table 27

IOCONCLKDIV5 R/W 0x138 Peripheral clock 5 to the IOCON block for

programmable glitch filter

0x0000 0000 Table 27

IOCONCLKDIV4 R/W 0x13C Peripheral clock 4 to the IOCON block for

programmable glitch filter

0x0000 0000 Table 27

IOCONCLKDIV3 R/W 0x140 Peripheral clock 3 to the IOCON block for

programmable glitch filter

0x0000 0000 Table 27

IOCONCLKDIV2 R/W 0x144 Peripheral clock 2 to the IOCON block for

programmable glitch filter

0x0000 0000 Table 27

IOCONCLKDIV1 R/W 0x148 Peripheral clock 1 to the IOCON block for

programmable glitch filter

0x0000 0000 Table 27

IOCONCLKDIV0 R/W 0x14C Peripheral clock 0 to the IOCON block for

programmable glitch filter

0x0000 0000 Table 27

BODCTRL R/W 0x150 Brown-Out Detect 0 Table 28

SYSTCKCAL R/W 0x154 System tick counter calibration 0x0 Table 29

- R/W 0x168 Reserved - -

IRQLATENCY R/W 0x170 IQR delay. Allows trade-off between interrupt

latency and determinism.

0x0000 0010 Table 30

NMISRC R/W 0x174 NMI Source Control 0 Table 31

PINTSEL0 R/W 0x178 GPIO Pin Interrupt Select register 0 0 Table 32

PINTSEL1 R/W 0x17C GPIO Pin Interrupt Select register 1 0 Table 32

PINTSEL2 R/W 0x180 GPIO Pin Interrupt Select register 2 0 Table 32

PINTSEL3 R/W 0x184 GPIO Pin Interrupt Select register 3 0 Table 32

PINTSEL4 R/W 0x188 GPIO Pin Interrupt Select register 4 0 Table 32

PINTSEL5 R/W 0x18C GPIO Pin Interrupt Select register 5 0 Table 32

PINTSEL6 R/W 0x190 GPIO Pin Interrupt Select register 6 0 Table 32

PINTSEL7 R/W 0x194 GPIO Pin Interrupt Select register 7 0 Table 32

STARTERP0 R/W 0x204 Start logic 0 pin wake-up enable register 0 Table 33

STARTERP1 R/W 0x214 Start logic 1 interrupt wake-up enable

0 Table 34

Table 5. Register overview: System configuration (base address 0x4004 8000) …continued

Name Access Offset Description Reset value Reference

User manual Rev. 1.2 — 14 March 2013 20 of 337

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Chapter 4: LPC800 System configuration (SYSCON)

4.6.1 System memory remap register

The system memory remap register selects whether the exception vectors are read from

boot ROM, flash, or SRAM. By default, the flash memory is mapped to address

0x0000 0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1,

the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory

map (addresses 0x0000 0000 to 0x0000 0200).

4.6.2 Peripheral reset control register

The PRESETCTRL register allows software to reset specific peripherals. A zero in any

assigned bit in this register resets the specified peripheral. A 1 clears the reset and allows

the peripheral to operate.

PDSLEEPCFG R/W 0x230 Power-down states in deep-sleep mode 0xFFFF Table 35

PDAWAKECFG R/W 0x234 Power-down states for wake-up from

deep-sleep

0xEDF0 Tab le 36

PDRUNCFG R/W 0x238 Power configuration register 0xEDF0 Table 37

DEVICE_ID R 0x3F8 Device ID part dependent Table 38

Table 5. Register overview: System configuration (base address 0x4004 8000) …continued

Name Access Offset Description Reset value Reference

Table 6. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit

description

Bit Symbol Value Description Reset

value

1:0 MAP System memory remap. Value 0x3 is reserved. 0x2

0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot

ROM.

0x1 User RAM Mode. Interrupt vectors are re-mapped to Static

RAM.

0x2 User Flash Mode. Interrupt vectors are not re-mapped and

reside in Flash.

31:2 - - Reserved -

Table 7. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

0 SPI0_RST_N SPI0 reset control 1

0 Assert the SPI0 reset.

1 Clear the SPI0 reset.

1 SPI1_RST_N SPI1 reset control 1

0 Assert the SPI1 reset.

1 Clear the SPI1 reset.

2 UARTFRG_RST_N USART fractional baud rate generator

(UARTFRG) reset control

0 Assert the UARTFRG reset.

1 Clear the UARTFRG reset.

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