Radix-4加法器性能优化与比较分析

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“Performance analysis of radix-4 adders.pdf”这篇文档是对基于 Carry 的Radix-4加法器的性能分析，作者是Shahzad Asif和Mark Vesterbacka，分别来自COMSAT SIIT和Linköping University。文章经过多次修订后在2011年发表，关键词包括CMOS全加器、Radix-4加法器、功耗-延迟乘积（Power-Delay Product，PDP）、能量-延迟乘积（Energy-Delay Product，EDP）以及基于进位的加法器。文章摘要指出，作者提出了一种静态CMOS全加器电路设计，该设计使用了Radix-4架构，能在传播延迟、PDP和EDP方面优于传统的Radix-2 Ripple Carry Adder。通过在晶体管级应用进位预取技术，他们实现的Radix-4电路在45纳米CMOS工艺下，在1.1V电源电压下进行SPICE仿真，结果显示其速度比2位Radix-2 Ripple Carry Adder快24%，同时晶体管数量仅略有增加，而功率消耗几乎保持不变。此外，他们还研究了一种减少加法器进位路径中晶体管数量的Radix-2和Radix-4加法器设计方案。在加法器的设计中，Radix-2和Radix-4是两种不同的进制表示方法。Radix-2（二进制）是最基础的加法方式，通常采用Ripple Carry Adder（逐位进位加法器），其中每个位都需要等待前一位的进位结果才能计算当前位。这种加法器结构简单，但因为进位延迟，整体速度相对较慢。而Radix-4加法器利用了四位一组的运算，可以并行处理多个位，减少了进位延迟，从而提高了运算速度。进位预取（Carry Look-Ahead）技术是提高加法器性能的重要手段之一，它通过提前计算出多位的进位，避免了逐位等待进位的延迟。这种技术在晶体管级实现，能够显著降低加法器的延迟时间。功耗-延迟乘积（PDP）和能量-延迟乘积（EDP）是衡量集成电路性能的重要指标。PDP是单次操作的延迟时间和功率消耗的乘积，而EDP则考虑了操作次数，因此更能反映实际应用中的能效。通过优化设计，使得PDP或EDP减小，意味着电路在保持速度的同时降低了能耗。 "Performance analysis of radix-4 adders.pdf"这篇论文探讨了如何通过采用Radix-4结构和进位预取技术来优化加法器性能，尤其是降低延迟和提高能效，这对于高速计算和低功耗电子设备的设计具有重要意义。同时，研究还涉及了减少进位路径中晶体管数量的方法，这进一步减小了电路规模，有利于集成度的提升。

Performance analysis of radix-4 adders

Shahzad Asif

, Mark Vesterbacka

Department of EE, COMSATS IIT, 44000 Islamabad, Pakistan

Department of EE, Link

oping University, SE-581 83 Link

oping, Sweden

article info

Article history:

Received 30 May 2011

Received in revised form

28 September 2011

Accepted 30 September 2011

Available online 13 October 2011

Keywords:

CMOS full adder

Radix-4 adder

Power-delay product

Energy-delay product

Carry-based adder

abstract

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in

carry-based adders compared with using a standard radix-2 full adder solution. The improvements are

obtained by employing carry look-ahead technique at the transistor level. Spice simulations using

45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4

circuit is 24% faster than a 2-bit radix-2 ripple carry adder with slightly larger transistor count, whereas

the power consumption is almost the same. A second scheme for radix-2 and radix-4 adders that have a

reduced number of transistors in the carry path is also investigated. Simulation results also conﬁrm that

the radix-4 adder gives better performance as compared to a standard 2-bit CLA. 32-Bit ripple carry,

2-stage carry select, variable size carry select, and carry skip adders are im plemented with the different

full adders as building blocks. There are PDP savings, with one exception, for the 32-bit adders in the

range 8–18% and EDP savings in the range 21–53% using ra dix-4 as compared to radix-2.

1. Introduction

Addition is the most basic and most frequently used operation

in digital circuit design [1,2]. Due to this reason, a large number of

adder architectures have been designed to accommodate the

requirements of different applications. Common parameters that

measure the performance of a circuit are speed, power, area,

power-delay product (PDP), and energy-delay product (EDP),

where the PDP represents the energy dissipation per switching

event and the EDP is a commonly used measure for energy-

performance trade-off [3,4]. On the basis of area and speed, we

can divide the adders in three major categories. The ripple carry

adder (RCA) is the slowest architecture with the least number of

transistors. The carry look-ahead adder (CLA) is the fastest adder

but requires very large area. The carry select adder (CSEL) is used

when we need a moderate solution [5–7]; it is faster than RCA but

slower than CLA.

Extensive research has been done to improve the performance

of the full adder (FA), which is the basic building block for large

carry-based adders. In [8–11], different architectures have been

presented to improve the performance of the FA in terms of speed,

power, and energy. In [12], different FA architectures are analyzed

and compared with respect to speed, power consumption and

PDP. In [13,14], different radix-2 and radix-4 architectures are

presented and compared for 64-bit parallel preﬁx adders with

main emphasis on the Kogge–Stone adder.

In this work, we design a radix-4 FA instead of the more

common radix-2 FA. The radix-4 FA is based on internal carry

look-ahead to reduce the carry propagation path in an adder since

that path is critical [3] . The main disadvantage of this architecture

is a slight increase in transistor count.

With the scaling of technology and supply voltage, it is

becoming more important to design the circuits having full

voltage swing, which results in high noise margins. For low power

applications, it is also common to reduce the supply voltage,

but doing so will result in even lower noise margins [15]. Static

CMOS logic provides high gain and a voltage swing equal to the

supply voltage, yielding high noise margins. Hence, the CMOS

logic style is a good choice for low power implementation in

deep submicron technologies [16], which we have chosen for

our design.

The paper is organized as follows. In Section 2, we study

different FA topologies. In Section 3, two radix-4 FAs are pro-

posed. In Sections 4 and 5, we discuss 32-bit adders that are

implemented for comparison. Section 6 shows the simulation

results of the adders, and the work is concluded in Section 7.

2. FA topology

In this work we focus on static CMOS circuits, which provide the

high noise margins required for implementation in deep submicron

technologies. A popular topology is the mirror FA [12], which is used

Contents lists available at SciVerse ScienceDirect

journal home page: www.elsevier.com/locate/vlsi

INTEGRATION, the VLSI journal

doi:10.1016/j.vlsi.2011.09.004

Corresponding author.

E-mail addresses: shahzad_comsats@yahoo.com (S. Asif),

markv@isy.liu.se (M. Vesterbacka).

INTEGRATION, the VLSI journal 45 (2012) 111–120

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