单片机类毕业论文设计-英文翻译.doc: A Modelling-Based Methodology for Evaluating Real-Time Embedded Control System Performance at Henan University of Science and Technology Undergraduate Thesis (Dissertation) 1 Embedded Systems Design and Embedded Control System Transformation Bridge by Klemen Perko, Remy Kocik, Redha Hamouche, and Andrej Trost

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单片机类毕业论文设计-英文翻译.doc是一种建模基础的方法论，用于评估实时嵌入式控制系统的性能。该论文提出了一种基于建模的嵌入式控制系统（ECS）设计方法。与其开发一种新的ECS设计方法不同，我们建议通过将其与其他嵌入式系统设计领域的方法论相结合来升级现有方法。我们创建了在控制调度和硬件/软件（HW/SW）协同设计工具之间的转换桥梁。通过定义这个桥梁，我们实现了自动模型转换。因此，我们获得了更准确的时间行为模拟，不仅考虑实时软件，还考虑了硬件架构。这一方法有望在ECS的设计和评估中发挥重要作用。

河南科技大学本科毕业设计（论文）

creating domain-specific modelling and program synthesis environments. In

order to configure the GME to serve a specific domain, a suitable metamodel for

the abstract HW/SW co-design is defined. This specific metamodel is

conformant with the GME metamodelling language, called MetaGME, and is

based on Unified Modelling Language (UML) class diagrams and Object

Constraint Language (OCL) constraints. A defined metamodel contains all the

syntactic, semantic, and presentation information regarding the ASyMod domain

– i.e., which HW and SW concepts can be used to construct models, the

relationships that may exist among those concepts, how the concepts may be

organized and viewed by the modeller, and the rules governing the construction

of models [35]. The second part of ASyMod is a model interpreter that parses

the information from the graphical model into a textual description. The

obtained description complies with the simulation kernel. This kernel is the third

part of the ASyMod tool; it is based on a methodology presented in [6] and

provides the means for the temporal simulation of distributed systems on the

system level.

The simulation of the model provides temporal information about the SW

task executions, the HW resource usage, the contentions on the communication

devices and their impact on the task executions. The results are summarized in a

HW resource utilization table and statistical information about the execution

time (delays, jitter) for each task. Based on this information, the designers can

see how the HW and SW components interact and identify eventual bottlenecks

in the system.

The ASyMod tool can evaluate several different HW architectures and SW

implementations against the design constraints. It enables quick and efficient

design-space exploration in the early stages of the design process. The tool can

be used as in stand-alone form or incorporated into the system design tool-chain

by means of importing an abstract system model and exporting the

model-evaluation results in the XML (Extensible Mark-up Language) format.

河南科技大学本科毕业设计（论文）

events and SD

is the initial delay of the first event. PEGs can also be used for

generating one-time events. In this case, a very long period ST

should be set

(beyond the total simulation time) and the delay SD

is used to define when an

event should be generated. The ASyMod tasks are event-triggered tasks. An

ASyMod task is composed of a description of the HW resource usage for a

particular piece of the code and RT execution constraints for the deadline and

priority. The task can be expressed with a triple tAn (D

, L

, B

), where

is the task deadline, L

is the task priority and the boolean B

defines

whether the scheduler should be called at the end of the task execution. This is

discussed in more detail in Subsection 3.1.1 with a guideline (v). The task

execution can begin if the task is triggered with an event and if the scheduler,

based on the scheduling policy and task RT execution constraints, allows its

execution. After the task execution is finished, the task generates an event. The

task can be triggered by a PEG or by an event generated at the end of the

execution of some other task. The connections in a set Xs

((T

× T

) ∪ (S ×

)) define the event flow. Events can be produced by PEGs and by tasks and

consumed only by tasks. Each connection is defined with the pair xs

, t

where y

defines the event producer (task t

or PEG xs

) and t

is the event

consumer task. If a task is triggered by another task, this can be recognized as a

sequence of tasks. The period of their execution depends on the PEG that

triggers the first task in this sequence. Depending on this PEG, the tasks in the

sequence can be onek-time or periodically triggered.

2.2.3. Architecture graph in ASyMod

In ASyMod the HW architecture is defined with a concept of abstract

execution units and abstract communication units and information about how

these components are connected together. The HW components that perform

some data computation (e.g., processors, multipliers, filters, etc.) are modelled

as execution units, while the components that perform data transfer and storage

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