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Renesas SH72531 32位微控制器硬件手册
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更新于2024-07-15
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"Renesas(瑞萨电子)的SH72531是一款32位微控制器,内置了RISC(精简指令集计算机)SH-2A型CPU内核,以及系统配置所需的关键外围功能。这款微控制器常用于汽车电子、嵌入式系统和发动机控制领域。用户手册详细介绍了SH72531的硬件信息,包括其32位超级高速RISC引擎家族成员SH72531和相关的开发板如R5F72531KFPU和DR5F72531DKFPU。文档修订列表指出各版本的变更位置,提醒用户在使用时务必查看最新的产品信息,并通过官方网站获取更新。此外,瑞萨电子不承担因使用其产品或技术信息可能导致的第三方知识产权侵权责任,且未提供任何形式的专利、版权或其他知识产权许可。"
这篇文档详细阐述了Renesas SH72531微控制器的硬件特性,它采用了Renesas独特的RISC SH-2A架构,这是一种高效能的CPU核心,适合于处理复杂的系统任务。SH72531微控制器集成了多种必要的外围功能,简化了系统设计,减少了外部组件的需求,从而降低了整体成本并提高了系统的可靠性。
SH72531还配备了浮点单元(FPU),这使得该控制器能够快速处理浮点运算,这对于需要精确计算的汽车电子应用,如发动机控制,至关重要。文档中提到的R5F72531KFPU和DR5F72531DKFPU是与SH72531相关的开发板,它们为工程师提供了评估和开发基于SH72531系统的一个平台,有助于快速原型制作和调试。
用户手册强调,所有包含的信息都是发布日期的最新信息,但可能会有变动,因此建议在购买或使用前向Renesas销售办公室确认最新的产品信息。同时,用户应定期关注通过瑞萨电子网站披露的额外和不同的信息,以确保合规性和最佳实践。
此外,文档中的法律条款明确指出,瑞萨电子不对使用其产品或技术信息可能导致的第三方知识产权侵权承担任何责任。这意味着购买和使用这些产品的用户需自行负责确保不会侵犯任何第三方的专利、版权或其他知识产权。因此,在设计和实施基于SH72531的解决方案时,用户需要进行充分的法律尽职调查。
Page xvi of xxx
12.15 Overview of Timer C......................................................................................................... 400
12.15.1 Block Diagram of Timer C ................................................................................... 400
12.16 Description of Timer C Registers ...................................................................................... 402
12.16.1 Timer Start Register C (TSTRC) .......................................................................... 402
12.16.2 Noise Canceler Control Register C0 to C4 (NCCRC0 to NCCRC4).................... 403
12.16.3 Timer Control Registers C0 to C4 (TCRC0 to TCRC4)....................................... 405
12.16.4 Timer Status Registers C0 to C4 (TSRC0 to TSRC4) .......................................... 408
12.16.5 Timer Interrupt Enable Registers C0 to C4 (TIERC0 to TIERC4)....................... 411
12.16.6 Timer I/O Control Registers C0 to C4 (TIORC0 to TIORC4) ............................. 412
12.16.7 Timer Counters C0 to C4 (TCNTC0 to TCNTC4) ............................................... 415
12.16.8 General Registers C00 to C43 (GRC00 to GRC43).............................................. 416
12.16.9 Noise Canceler Counters C00 to C43 (NCNTC00 to NCNTC43)........................ 417
12.16.10 Noise Cancel Registers C00 to C43 (NCRC00 to NCRC43).............................. 419
12.17 Operations of Timer C ....................................................................................................... 420
12.17.1 Input Capture Function ......................................................................................... 420
12.17.2 Compare Match Function ..................................................................................... 421
12.17.3 PWM Function...................................................................................................... 423
12.18 Overview of Timer D......................................................................................................... 425
12.18.1 Block Diagram of Timer D................................................................................... 425
12.19 Description of Timer D Registers ...................................................................................... 427
12.19.1 Timer Start Register (TSTRD).............................................................................. 427
12.19.2 Timer Control Registers D0 to D3 (TCRD0 to TCRD3) ...................................... 428
12.19.3 Timer I/O Control Registers 1D0 to 1D3 (TIOR1D0 to TIOR1D3)..................... 431
12.19.4 Timer I/O Control Registers 2D0 to 2D3 (TIOR2D0 to TIOR2D3)..................... 434
12.19.5 Down Counter Starting Registers D0 to D3 (DSTRD0 to DSTRD3)................... 437
12.19.6 Down Counter Status Registers D0 to D3 (DSRD0 to DSRD3)........................... 438
12.19.7 Down Counter Control Registers D0 to D3 (DCRD0 to DCRD3) ....................... 440
12.19.8 Timer Status Registers D0 to D3 (TSRD0 to TSRD3) ......................................... 442
12.19.9 Timer Interrupt Enable Registers D0 to D3 (TIERD0 to TIERD3)...................... 448
12.19.10 Compare Match Pulse Output Control Registers D0 and D1
(CMPOD0 and CMPOD1) ................................................................................. 450
12.19.11 Timer Output Control Registers D0 to D3 (TOCRD0 to TOCRD3) .................. 451
12.19.12 Timer Offset Base Registers D0 to D3 (OSBRD0 to OSBRD3) ........................ 452
12.19.13 Timer Counter 1D0 to 1D3 (TCNT1D0 to TCNT1D3)...................................... 453
12.19.14 Timer Counters 2D0 to 2D3 (TCNT2D0 to TCNT2D3) .................................... 454
12.19.15 Output Compare Registers D00 to D33 (OCRD00 to OCRD33) ....................... 455
12.19.16 General Registers D00 to D33 (GRD00 to GRD33)........................................... 456
12.19.17 Timer Down Counters D00 to 33 (DCNTD00 to DCNTD33)............................ 457
12.20 Operations of Timer D....................................................................................................... 459
12.21 Overview of Timer E ......................................................................................................... 466
Page xvii of xxx
12.21.1 Block Diagram of Timer E ................................................................................... 466
12.22 Description of Timer E Registers....................................................................................... 469
12.22.1 Timer Start Register E (TSTRE)........................................................................... 469
12.22.2 Subblock Starting Registers E0 to E4 (SSTRE0 to SSTRE4)............................... 470
12.22.3 Prescaler Registers E0 to E4 (PSCRE0 to PSCRE4) ............................................ 472
12.22.4 Timer Control Register E0 to E4 (TCRE0 to TCRE4) ......................................... 473
12.22.5 Reload Control Registers E0 to E4 (RLDCRE0 to RLDCRE4) ........................... 474
12.22.6 Output Termination Control Registers E0 to E4 (POECRE0 to POECRE4)........ 475
12.22.7 Output Termination Level Setting Registers E0 to E4
(SOLVLE0 to SOLVLE4) .................................................................................... 476
12.22.8 Timer Status Registers E0 to E4 (TSRE0 to TSRE4) ........................................... 477
12.22.9 Timer Interrupt Enable Registers E0 to E4 (TIERE0 to TIERE4)........................ 480
12.22.10 Timer Output Control Registers E0 to E4 (TOCRE0 to TOCRE4) .................... 481
12.22.11 Timer Counters E00 to E43 (TCNTE00 to TCNTE43) ...................................... 482
12.22.12 Cycle-Setting Registers E00 to E43 (CYLRE00 to CYLRE43) ......................... 483
12.22.13 Duty Cycle Setting Registers E00 to E43 (DTRE00 to DTRE43)...................... 484
12.22.14 Cycle Reload Registers E00 to E43 (CRLDE00 to CRLDE43) ......................... 484
12.22.15 Duty Cycle Reload Registers E00 to E43 (DRLDE00 to DRLDE43) ................ 485
12.23 Operations of Timer E ....................................................................................................... 486
12.24 Overview of Timer F ......................................................................................................... 491
12.24.1 Block Diagram of Timer F.................................................................................... 492
12.24.2 Interrupts............................................................................................................... 493
12.25 Description of Timer F Registers....................................................................................... 494
12.25.1 Timer Start Register F (TSTRF)........................................................................... 494
12.25.2 Noise Canceller Control Register F (NCCRF)...................................................... 496
12.25.3 Timer Control Registers F0 to F19 (TCRF0 to TCRF19)..................................... 498
12.25.4 Timer Interrupt Enable Registers F0 to F19 (TIERF0 to TIERF19)..................... 501
12.25.5 Timer Status Registers F0 to F19 (TSRF0 to TSRF19)........................................ 502
12.25.6 Timer Counters AF0 to AF19 (ECNTAF0 to ECNTAF19).................................. 505
12.25.7 Event Counters F0 to F19 (ECNTBF0 to ECNTBF19) ........................................ 506
12.25.8 Time Counters CF0 to CF19 (ECNTCF0 to ECNTCF19).................................... 508
12.25.9 General Registers AF0 to AF19 (GRAF0 to GRAF19)........................................ 509
12.25.10 General Registers BF0 to BF19 (GRBF0 to GRBF19)....................................... 510
12.25.11 General Registers CF0 to CF19 (GRCF0 to GRCF19)....................................... 511
12.25.12 General Registers DF12 to DF15 (GRDF12 to GRDF15).................................. 512
12.25.13 Capture Output Registers F0 to F19 (CDRF0 to CDRF19) ................................ 513
12.25.14 Noise Canceler Counters FA0 to FA19 (NCNTFA0 to NCNTFA19) ................ 514
12.25.15 Noise Canceler Counters FB0 to FB2 (NCNTFB0 to NCNTFB2)..................... 516
12.25.16 Noise Cancel Registers FA0 to FA19 (NCRFA0 to NCRFA19)........................ 518
12.25.17 Noise Cancel Registers FB0 to FB2 (NCRFB0 to NCRFB2)............................. 519
Page xviii of xxx
12.26 Operations of Timer F........................................................................................................ 520
12.26.1 Edge Counting ...................................................................................................... 520
12.26.2 Valid Edge Interval Counting ............................................................................... 522
12.26.3 Measurement of Time during High/Low Input Levels ......................................... 523
12.26.4 Measurement of PWM Input Waveform Timing.................................................. 525
12.26.5 Rotation Speed/Pulse Measurement ..................................................................... 527
12.26.6 Up/Down Event Count.......................................................................................... 530
12.26.7 Four-time Multiplication Event Count.................................................................. 532
12.26.8 Overflow and Underflow ...................................................................................... 534
12.27 Overview of Timer G......................................................................................................... 535
12.27.1 Block Diagram of Timer G................................................................................... 535
12.27.2 Interrupt Requests................................................................................................. 535
12.28 Description of Timer G Registers ...................................................................................... 536
12.28.1 Timer Start Register G (TSTRG).......................................................................... 536
12.28.2 Timer Control Register G0 to G5 (TCRG0 to TCRG5) ....................................... 537
12.28.3 Timer Status Registers G0 to G5 (TSRG0 to TSRG5) ......................................... 538
12.28.4 Timer Counters G0 to G5 (TCNTG0 to TCNTG5) .............................................. 540
12.28.5 Compare Match Registers G0 to G5 (OCRG0 to OCRG5) .................................. 541
12.29 Operations of Timer G....................................................................................................... 542
12.30 Overview of Timer H......................................................................................................... 543
12.30.1 Block Diagram of Timer H................................................................................... 543
12.30.2 Interrupts............................................................................................................... 543
12.31 Description of Timer H Registers ...................................................................................... 544
12.31.1 Timer Control Register H (TCRH)....................................................................... 544
12.31.2 Timer Status Register H (TSRH).......................................................................... 545
12.31.3 Timer Counter 1H (TCNT1H).............................................................................. 547
12.31.4 Compare Match Register 1H (OCR1H)................................................................ 548
12.31.5 Timer Counter 2H (TCNT2H).............................................................................. 549
12.32 Operations of Timer H....................................................................................................... 550
12.33 Overview of Timer J.......................................................................................................... 551
12.33.1 Block Diagram of Timer J .................................................................................... 551
12.34 Description of Timer J Registers ....................................................................................... 552
12.34.1 Timer Start Register J (TSTRJ) ............................................................................ 552
12.34.2 Timer Control Registers J0 and J1 (TCRJ0 and TCRJ1)...................................... 553
12.34.3 FIFO Control Registers J0 and J1 (FCRJ0 and FCRJ1) ....................................... 556
12.34.4 Timer Status Register J0 and J1 (TSRJ0 and TSRJ1)........................................... 558
12.34.5 Timer Interrupt Enable Registers J0 and J1 (TIERJ0 and TIERJ1)...................... 562
12.34.6 Timer Counter J0 and J1 (TCNTJ0 and TCNTJ1)................................................ 563
12.34.7 Compare Match Registers J0 and J1 (OCRJ0 and OCRJ1) .................................. 563
12.34.8 FIFO Registers J0 and J1 (FIFOJ0 and FIFOJ1) .................................................. 564
Page xix of xxx
12.34.9 FIFO Data Count Registers J0 and J1 (FDNRJ0 and FDNRJ1) ........................... 565
12.34.10 Noise Canceler Counters J0 and J1 (NCNTJ0 and NCNTJ1)............................. 566
12.34.11 Noise Cancel Registers J0 and J1 (NCRJ0 and NCRJ1)..................................... 567
12.35 Operations of Timer J ........................................................................................................ 568
12.36 Usage Notes ....................................................................................................................... 571
12.36.1 Input Capture Conflict Operation ......................................................................... 571
12.36.2 Compare Match Conflict Operation...................................................................... 575
12.36.3 Load/Reload Conflict Operation........................................................................... 587
12.36.4 Counter Conflict Operation................................................................................... 590
12.36.5 Noise Canceler Conflict Operation....................................................................... 595
12.36.6 Conflict Regarding Down Counter D ................................................................... 598
12.36.7 Conflict between Timer B and Timer D ............................................................... 603
12.36.8 Compare-match Operation Specification.............................................................. 607
Section 13 Watchdog Timer (WDT)..................................................................609
13.1 Features.............................................................................................................................. 609
13.2 Input/Output Pin................................................................................................................. 611
13.3 Register Descriptions......................................................................................................... 611
13.3.1 Watchdog Timer Control Register (WTCR)......................................................... 611
13.3.2 Watchdog Timer Counter (WTCNT).................................................................... 614
13.3.3 Watchdog Timer Status Register (WTSR)............................................................ 615
13.3.4 Watchdog Reset Control Register (WRCR) ......................................................... 617
13.3.5 Notes on Register Access...................................................................................... 619
13.4 WDT Usage .......................................................................................................................620
13.4.1 Using WDT in Watchdog Timer Mode ................................................................ 620
13.4.2 Using WDT in Interval Timer Mode .................................................................... 622
13.5 Usage Notes ....................................................................................................................... 623
13.5.1 Timer Error ........................................................................................................... 623
13.5.2 Changing of Division Ratio .................................................................................. 623
13.5.3 Switching between Watchdog and Interval Timer Modes .................................... 623
13.5.4 System Reset by WDTOVF Signal....................................................................... 624
Section 14 Compare Match Timer (CMT) ........................................................625
14.1 Features.............................................................................................................................. 625
14.2 Register Descriptions......................................................................................................... 626
14.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 627
14.2.2 Compare Match Timer Control Register (CMCR) ............................................... 628
14.2.3 Compare Match Timer Status Register (CMSR) .................................................. 629
14.2.4 Compare Match Counter (CMCNT) ..................................................................... 630
14.2.5 Compare Match Constant Register (CMCOR) ..................................................... 630
Page xx of xxx
14.3 Operation ........................................................................................................................... 631
14.3.1 Interval Count Operation ...................................................................................... 631
14.3.2 CMCNT Count Timing......................................................................................... 631
14.4 Interrupts............................................................................................................................ 632
14.4.1 Interrupt Sources and DMA Transfer Requests.................................................... 632
14.4.2 Timing of Compare Match Flag Setting ............................................................... 632
14.4.3 Timing of Compare Match Flag Clearing............................................................. 633
14.5 Usage Notes ....................................................................................................................... 634
14.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................... 634
14.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 635
14.5.3 Conflict between Setting of Compare-Match Flag and Clearing by the CPU ...... 636
Section 15 Serial Communications Interface (SCI) ..........................................637
15.1 Features.............................................................................................................................. 637
15.2 Input/Output Pins...............................................................................................................639
15.3 Register Description .......................................................................................................... 640
15.3.1 Receive Shift Register (SCRSR1) ........................................................................ 641
15.3.2 Receive Data Register (SCRDR1)........................................................................ 641
15.3.3 Transmit Shift Register (SCTSR1) ....................................................................... 642
15.3.4 Transmit Data Register (SCTDR1)....................................................................... 642
15.3.5 Serial Mode Register (SCSMR1).......................................................................... 643
15.3.6 Serial Control Register (SCSCR1)........................................................................ 646
15.3.7 Serial Status Register (SCSSR1) .......................................................................... 650
15.3.8 Bit Rate Register (SCBRR1) ................................................................................ 656
15.4 Operation ........................................................................................................................... 662
15.4.1 Overview .............................................................................................................. 662
15.4.2 Operation in Asynchronous Mode........................................................................ 664
15.4.3 Clock Synchronous Mode..................................................................................... 673
15.5 SCI Interrupt Sources and A-DMAC................................................................................. 682
15.6 Usage Notes ....................................................................................................................... 683
15.6.1 SCTDR1 Writing and TDRE Flag........................................................................ 683
15.6.2 Multiple Receive Error Occurrence...................................................................... 683
15.6.3 Break Detection and Processing ........................................................................... 684
15.6.4 Sending a Break Signal......................................................................................... 684
15.6.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)...... 684
15.6.6 Note on Using A-DMAC...................................................................................... 686
15.6.7 Note on Using External Clock in Clock Synchronous Mode................................ 686
15.6.8 Note on Using A-DMAC...................................................................................... 686
15.6.9 Serial Ports............................................................................................................ 687
15.6.10 Note on Reception Only, with SCK Output, in Clock Synchronous Mode .......... 687
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