Preliminary Spec. for NT39016E
TFT LCD Driver
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8
Version 0.5 Nov 7 ,2008
Pad Description
NT39016 Pad Description:
Designation I/O Description
DIN[23..0] I
Data Input. For 8/24-bit digital (RGB) or 8-bit CCIR601/656 image data input
8-bit mode: DIN7: MSB; DIN0: LSB; the remainder should be connect to GND.
24-bit mode: DIN[7:0] = R[7:0] data; DIN[15:8] = G[7:0] data; DIN[23:16] = B[7:0] data.
For 18bit RGB interface, connect two LSB bits of all the R/G/B data bus to GND.
CLKIN I
Clock for Input Data. Data latched at rising/falling edge of this signal. Default
polarity.
HSD I/O
Horizontal Sync I/O. Default Negative polarity, can be change by HSDPOL register.
Please floating VSD & HSD under
CCIR656 and
DE mode.
VSD I/O
Vertical Sync I/O. Default Negative polarity, can be change by VSDPOL register.
Please floating VSD & HSD under
CCIR656 and
DE mode.
DEN
I
(Pull Low)
Data Enable signal Input . Active High to enable the data input Bus under “DE Mode
Normally pull low.
DATSEQ O
Data sequence control pin for external T-CON.
Output “1”: for Odd line, “0”: for Even line
POL O Frame polarity output. Amplitude of signal is from 0V to 3.3V.
V1 ~ V7 I/O
Gamma correction reference voltage.
When VSET=”1” is used. The voltage of pins V1 ~ V7 must be swing and must be
AVDD-0.1V > V1 > V2 > V3 V5 > V6 > V7 > AGND+0.1V when POL=”1” and
AGND+0.1V < V1’ < V2’ < V3’ V5’ < V6’ < V7’ < AVDD-0.1V when POL=”0”,
Where V1-V2=V2’-V1’, V2-V3=V3’-V2’, …V5-V6=V6’-V5’, V6-V7=V7’-V6’.
Note: V1~V7
must be supplied voltage external when VSET=”1”. Vx is external power of
positive polarity and Vx’ is external power of negative polarity
SPENB
I
(Pull High)
3-Wire Communication Enable. Active Low. Normally pull high.
Please pull high or floating under PINCTLB=0 mode.
SPDA I/O 3-Wire Communication Data input/output.
SPCK I 3-Wire Communication Clock input. Rising edge latch.
SPSW
I
(Pull Low)
3-Wire register map select.
”0” for default 3-Wire register map, “1” for optional 3-Wire register map.
RSTB
I
(Pull High)
Global reset pin. Active Low to enter Reset State. Suggest connecting
circuit for stability. Normally pull high.
PINCTLB
I
(Pull High)
Enable pin control function. Normally pull high
PINCTLB = “0”, Enable pin control function.
TP0~TP18 active as input pin for function
control propose. Refer to the TP0~18 description for more information.
PINCTLB = “1”, Default mode. TP0~TP18 active as unknown state ; Don’
to any state under this mode.
Note: The 3-wire control register will be disabled under PINCTLB = 0 mode.
SO1~SO960 O Source Driver Output Signals.
GO1~GO240 O Gate Driver Output Signals.
ALIGN_T/B M For assembly alignment.
TP0 ~ 18
T
I
TEST Pin / Function control pin.
When PINCTLB = “1”, TP0~18 act as test pin. Floating those pins for normal operation.
When PINCTLB = “0”
, TP0~18 act as function control input pin. All the input pin should be
connect to GND or VDD. Floating those pins will result in input unknown problem.
VPSW
I
(Pull Low)
Voltage control switch. Normally pull low.
VPSW = “0” .Default mode. VGH
、
VGL
、
VCOMAC and VCOMDC active as normal use and
control by 3-wire.
VPSW = “1”.Voltage fix mode. VGH = 18V
、
VGL = -7V
、
= 1.7V. Under the mode voltage can't control by 3-wire
VPP_OTP P Customer OTP power input pin
VGH PS Capacitor pin. Positive power supply for Gate Driver output
VGL PS Capacitor pin. Negative power supply for Gate Driver output