ADS1293：低功耗生物信号测量模拟前端

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"ADS1293是一款专用于生物电位测量的低功耗模拟前端(AFE)，适用于心电传感器(ECG)应用。这款芯片具备3个高分辨率通道，每个通道都具有同步起搏输出功能，能以最高25.6ksps的速率工作。ADS1293设计集成了抗电磁干扰(EMI)输入滤波器，确保在复杂环境中稳定工作。其低功耗特性每个通道仅为0.3mW，输入噪声低至7μVpp（40Hz带宽），输入偏置电流仅为175pA。" ADS1293的主要特性包括： 1. **3个高分辨率ECG通道**：每个通道都能独立编程设置采样率和带宽，提供灵活性以适应不同的性能和功耗需求。 2. **抗EMI输入**：内置滤波器有助于减少电磁干扰对信号的影响，提高测量的准确性和可靠性。 3. **低功耗设计**：每个通道仅消耗0.3mW，适合电池供电的便携式设备。 4. **输入噪声和偏置电流控制**：7μVpp的输入噪声和175pA的输入偏置电流，确保了高精度的信号采集。 5. **宽范围的差分输入电压**：支持±400mV的输入范围，适应不同信号幅度的测量需求。 6. **模拟电源和数字I/O电源电压**：模拟电源电压为2.7V至5.5V，数字I/O电源电压为1.65V至3.6V，具有较宽的工作电压区间。 7. **右腿驱动放大器**：支持右腿驱动(RLD)技术，有助于消除身体内部噪声。 8. **导联断线检测**：集成的交流和直流导联断线检测功能，确保信号质量。 9. **Wilson和Goldberger终端**：提供Wilson/Goldberger基准电端，方便实现不同类型的ECG测量。 10. **外部模拟起搏检测**：第四个通道可以用于检测外部模拟起搏信号，适用于不需要数字起搏检测的应用。 11. **自我诊断警报系统**：通过ALARMB引脚报告系统异常，提高系统的可靠性。 12. **电池电压监控**：内置功能监测电池电压，帮助维护系统的正常运行。 13. **灵活的断电和待机模式**：可选择合适的电源管理模式，进一步降低功耗。此外，ADS1293通过SPI总线与微控制器(MCU)通信，便于系统集成和控制。它提供了全面的技术文档、工具软件及社区支持，便于开发人员进行产品设计和问题解决。ADS1293是设计高性能、低功耗心电图监测系统时的理想选择，尤其适合医疗、体育运动和健身领域。

CH1-ECG

CH2-ECG

CH3-ECG

Lead off

detect

EMI

filter

CSB

SCLK

SDI

SDO

OSC

IN1

Flexible

Routing

Switch

Test

Ref

XTAL1

VSS

VDD

VDDIO

CVREF

RLDINV

RLDIN

EMI

filter

IN2

EMI

filter

IN3

EMI

filter

IN4

EMI

filter

IN5

EMI

filter

IN6

Batt.

Mon

CMOUT

XTAL2

POR

RSTB

DRDYB

RLDREF

RLDOUT

CLK

ALARMB

DIGITAL

CONTROL AND

POWER

MANAGEMENT

Wilson

ref.

Detect

SYNCB

VSSIO

Digital

Filter

Σ∆

Modulator

Digital

Filter

Σ∆

Modulator

InA

WCT

CH4- Analog Pace

WILSON_EN

CMDET_EN

SELRLD

REF

EMI

filter

EMI

filter

LOD_EN

CH1-Pace

CH2-Pace

CH3-Pace

Digital

Filter

Σ∆

Modulator

REF for

CM & RLD

RLD

Amp.

PACE2

RLDIN

PACE2WCT

WILSON_CN

CH1

CH2

CH3

CH4 InA

ADS1293

www.ti.com.cn

ZHCSA21C –FEBRUARY 2013–REVISED DECEMBER 2014

8 Detailed Description

8.1 Overview

The ADS1293 is a fully-integrated signal chain for ECG applications. It features three low-power, 24-bit resolution

channels for ECG and pace monitoring and an auxiliary fourth channel for analog pace detection. In addition, the

ADS1293 features AC and DC lead-off detection, right-leg drive capability, and Wilson and Goldberger terminals.

Each of the three channels is synchronized and provides digital filtering with a cut-off frequency that is

programmable from 5 Hz to 1280 Hz. Each channel filter can be set independently while maintaining

synchronization. In addition, a lower-resolution output is provided for each signal channel with a cut-off frequency

programmable between 650 Hz to 2.6 kHz. These output signals are ideal for sensing a pace-maker signal. Each

channel provides enough dynamic range to handle electrode offset and motion artifacts without sacrificing

resolution. Each input has built-in EMI rejection that eliminates noise from RF transmitters.

8.2 Functional Block Diagram

IN3

IN4

IN1

IN2

IN5

IN6

POSx

CALx=11

NEGx

INP_CHx

INN_CHx

VDD

CVREF

TSTx=10

TSTx=01

VREFP

VREFN

VBAT_MONI_CHx

ADS1293

ZHCSA21C –FEBRUARY 2013–REVISED DECEMBER 2014

www.ti.com.cn

8.3 Feature Description

8.3.1 Flexible Routing Switch

The flexible routing switch can connect the inputs of the three analog front-end channels as well as the inputs of

the analog pace channel to any of the 6 input pins. This allows system flexibility and even on-the-fly

reconfiguration of the ECG monitoring system. For test purposes, the flexible routing switch can short the

differential input pins of a channel or connect a differential reference signal to the input of a channel. This

reference voltage can be applied with both positive and negative polarity. This feature allows to measure relative

mismatches between channels, such as offset and gain mismatches. Additionally, there is an option to route a

fraction of the battery voltage (the voltage source connected to the VDD pin) to an input channel. This allows the

ADS1293 to monitor the state of charge of the battery.

The switch path inside the flexible routing switch is illustrated in Figure 17. The figure shows the switch path for a

single channel. All channels are completely identical. The switches are controlled by the registers

FLEX_CH1_CN, FLEX_CH2_CN, FLEX_CH3_CN, and FLEX_VBAT_CN, which are described in the Input

Channel Selection Registers.

Figure 17. Flexible Routing Switch for Channel 1

It should be noted that the switches that control the input selection for the analog front-end channels have a

certain priority. If the battery voltage monitoring mode is enabled by programming the VBAT_MONI_CHx bit in

the FLEX_VBAT_CN register, then the POSx and NEGx bits programmed in the FLEX_CHx_CN register no

longer have any effect. The battery voltage monitoring mode thus takes priority; this is shown in the first row of

Table 1. Furthermore, the test features take second priority over the input pin selection. If the TSTx bit of the

FLEX_CHx_CN register are not zero, then the POSx and NEGx bits are essentially ignored, and the test features

will take priority as seen in Table 1. The TSTx, POSx, and NEGx bits are described in the Input Channel

Selection Registers.

Table 1. Channel 1 Switch Configuration

VBAT_MONI_CHx CALx POSx NEGx MODE

1 X X X CHx is in battery voltage monitoring mode

0 11 X X CHx input shorted

0 01 X X CHx input connected to positive reference

0 10 X X CHx input connected to negative reference

CHx positive input connected to pin INx and negative input connected to pin

0 00 INx INy

INy

OUT MAX

ADC ADC

TEST

OUT MAX

REF

3.5 V

ADC ADC

2 V 2

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www.ti.com.cn

ZHCSA21C –FEBRUARY 2013–REVISED DECEMBER 2014

Feature Description (continued)

8.3.2 Battery Monitoring

The battery voltage monitoring mode is enabled by setting bit VBAT_MONI_CHx = 1 in the FLEX_VBAT_CN

SHDN_INA_CHx = 1 in the AFE_SHDN_CN register. In this mode, the positive input, POSx, of the sigma-delta

modulator will sample the voltage supplied on the VDD pin. At the same time, the negative input, NEGx, of the

sigma-delta modulator will sample the reference voltage, V

REF

, generated on or provided to the CVREF pin. As a

result, the output signal of the sigma-delta modulator is a measure for (V

BAT

-V

REF

). In this operation, the sigma-

delta modulator works with a modified gain factor, and the battery voltage, V

BAT

, can be calculated as follows:

(1)

In this equation, V

REF

equals 2.4 V if the internal reference voltage generator is used, and ADC

MAX

represents

the maximum output code of the ADC, which would correspond to a theoretical 2.4-V signal at the input of the

sigma-delta modulator. The value of ADC

MAX

is dependent on the configuration of the digital filters, and the

corresponding ADC

MAX

values are listed in Table 8 through Table 11.

The battery monitoring mode is targeted for battery operated systems within a voltage range of 2.4 V to 4.8 V.

The battery monitoring mode cannot be used when the ADS1293 is powered from a regulated 5-V supply

because it risks saturating the sigma-delta modulator. There is a also a low battery alarm that is implemented

independently from the battery monitoring mode, which will trigger a battery alarm when the supply voltage is

below 2.7 V (see the BATLOW description in Alarm Functions).

8.3.3 Test Mode

If the battery voltage monitoring function is not enabled, and if bit TSTx = 01 (see the Input Channel Selection

Registers section), then a positive DC test signal is provided to the input of the instrumentation amplifier. If TSTx

= 10, then that same test signal is provided but with negative polarity. The expected ADC output code can be

calculated as follows:

(2)

In Equation 2, the positive or negative DC test signal V

TEST

= V

REF

/12. Note that this test mode is not a gain

calibration since V

TEST

and V

REF

are generated by the same reference; however, it can be used as a self-test or

to measure gain mismatches between channels.

When TSTx = 11, the inputs of the instrumentation amplifier in the channel can be shorted to provide a zero test

signal. The expected ADC output code equation can be simplified to:

(3)

For both equations, the value of ADC

MAX

corresponding to a given decimation configuration can be obtained from

Table 8 through Table 11.

8.3.4 Analog Front-End

The ADS1293 contains three analog front ends that convert a differential analog voltage into a digital signal.

Each analog front end consists of an instrumentation amplifier (INA), a sigma-delta modulator (SDM), and a

digital filter.

8.3.5 Instrumentation Amplifier (INA)

The instrumentation amplifier provides a high input impedance to interface with signal sources that may have

relatively high output impedance, such as ECG electrodes. The maximum differential input voltage range of the

Sigma-Delta Modulator (SDM) behind the INA is ±1.4 V, and the gain of the INA is 3.5x. Therefore, the maximum

differential input voltage of the INA is ±400 mV.

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ADS1293

ZHCSA21C –FEBRUARY 2013–REVISED DECEMBER 2014

www.ti.com.cn

Feature Description (continued)

The input common-mode voltage range (CMVR) of the INA is 0.95 V to VDD-0.95 V. If the input differential

voltage range is limited to smaller values, then the CMVR can be somewhat extended. If the differential input

signal is limited to VIN

MAX

, the CMVR range can be defined as:

(4)

The INA can be configured to operate in a low-power mode or in a high-resolution mode. The low-power mode

consumes about 3 times less power than the high-resolution mode. However, the high-resolution mode has less

noise than the low-power mode. Switching between these two modes is controlled by the EN_HIRES_CHx bits in

the AFE_RES register.

When a channel is not in use, its INA can be shut down by programming the SHDN_INA_CHx bit in the

AFE_SHDN_CN register, and its SDM can also be shut down by programming the SHDN_SDM_CHx bit in the

AFE_SHDN_CN register.

8.3.5.1 Instrumentation Amplifier Fault Detection

The output signal of the instrumentation amplifier can be monitored to ensure its output signal is within an

appropriate range. The out-of-range error flags for the INAs can be observed in the ERROR_RANGE1,

ERROR_RANGE2 and ERROR_RANGE3 registers.

The output signal is present at two points: OUTP and OUTN. If the input common-mode voltage or differential

voltage is such that the instrumentation amplifier would have to drive the voltages at these points above the

positive or below the negative supply rail, then the signal accuracy would be lost. These two points are monitored

and a warning flag is raised if the voltage on these pins approaches the supply rails. If the OUTP_HIGH flag is

raised, then the voltage at OUTP is close to the positive rail. This indicates the differential input signal is too

large or the input common-mode voltage is too high. If the OUTP_LOW flag is raised, then the voltage at OUTP

is close to the negative rail. This happens at low input common-mode voltages and large negative differential

input voltages. Similar reasoning holds for the OUTN_HIGH and OUTN_LOW flags.

The differential output voltage of the INA is monitored and reported to the DIF_HIGH bit. This error flag indicates

that the differential signal is out-of-range and is no longer an accurate representation of the input signal. The

DIF_HIGH error flag is raised if the differential output voltage of the INA exceeds ±1.4 V, which is the input range

of the Delta-Sigma Modulator. When this happens, the SDM will no longer sample the output of the INA, but

instead will sample 0 V. The sign of the input signal can still be observed in the SIGN bit of the

ERROR_RANGEx registers.

The fault detection circuitry for OUTP_HIGH, OUTP_LOW, OUTN_HIGH and OUTN_LOW can be shut down by

programming the SHDN_FAULTDET_CHx bits in the AFE_FAULT_CN register. These shutdown bits do not

affect the operation of DIF_HIGH and SIGN because the instrumentation amplifier should always provide these

signals to the sigma-delta modulator. The circuitry that generates DIF_HIGH and SIGN only gets shut down

when the corresponding INA is shut down.

8.3.6 Sigma-Delta Modulator (SDM)

The Sigma-Delta Modulator (SDM) takes the output signal of the INA and converts this signal into a high

resolution bit stream that is further processed by the digital filters.

The SDM can operate at clock frequencies of 102.4 kHz or 204.8 kHz; these frequencies are generated

internally. Running the SDM at 204.8 kHz results in a larger oversampling ratio, which improves the resolution of

the signal recovered by the digital filters behind the SDM. However, running the SDM at a higher clock frequency

will increase its power consumption, resulting in a tradeoff between resolution and power consumption.

The 102.4-kHz or 204.8-kHz clock frequency can be selected for each channel individually by programming the

FS_HIGH_CHx bits in the AFE_RES register.

The SDM also features dithering to reduce tones in the system, a known by-product of Sigma-Delta converters.

The dithering circuit is active by default and is automatically turned OFF when the input signal is larger than 40

mV.

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