"PCIe 4.0协议文档：PHY测试规范及PCIe标准"

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PCIe4.0 PHY测试规范是PCIe4.0协议文档中的一部分，该协议是PCIe标准协议的一部分。该规范的全称是“PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.01”。该规范的最新修订日期是2020年4月7日。首先，PCI-SIG®在该文档中声明放弃所有的担保和责任，并不对文档中可能出现的错误承担责任。同时，PCI-SIG®也不保证对文档中的信息进行更新。如果需要获取该规范的最新版本，请联系PCI-SIG办公室。 PCIe4.0 PHY测试规范是针对PCI Express体系结构PHY的测试的详细说明。PHY（Physical Layer）是PCIe协议中的物理层，主要负责数据传输的物理转换以及电信号的发送和接收。该规范对PCIe4.0 PHY的测试要求进行了详细描述。测试要求包括接收端和发送端的测试，以及相关测试设备和测试方法的介绍。对于接收端的测试，规范要求验证接收链路的性能，包括接收链路的等化、时钟恢复、信号眼图等性能参数的测试。对于发送端的测试，规范要求验证发送链路的性能，包括发送链路的预编码和电压波形等性能参数的测试。此外，规范还包括了测试设备的要求，包括测试仪器的类型、性能指标和连接方式等。同时，规范也描述了不同测试方法的步骤和参数设置，以确保测试的准确性和可靠性。最后，规范强调了PCI-SIG®对于该规范的所有权和版权，并对使用该规范的风险进行了提醒。同时，规范强调了对于PCIe Express体系结构PHY相关问题的咨询，可联系PCI-SIG办公室。综上所述，PCIe4.0 PHY测试规范是PCIe4.0协议文档的一部分，旨在对PCI Express体系结构PHY进行测试，并对测试要求、测试设备和测试方法进行了详细描述。通过遵守该规范，可以确保PCIe4.0 PHY的性能和可靠性，从而保证数据传输的高速和稳定。

Test Descriptions

PCI Express Architecture PHY Test Specification | 12

Revision 4.0, Version 1.01

April 7, 2020

9. Measure Uncorrelated PWJ Tj @ E-12 using the SigTest analysis program with the 16 GT/s

Pulse Width Jitter template file (PCIE_4_0_CARD\ PCIe_4_16GB_Tx_PWJ.dat).

Note: This measurement is performed with a 16 GT/s toggle (1010) pattern. The

-12 dB behavioral CTLE is applied to the waveform as indicated in the PCI Express Card

Electromechanical Specification. Applying the CTLE is more representative of the signal

present at the Rx latch.

10. If the SigTest analysis program indicates the Add-in Cards Uncorrelated PWJ Tj @ E-12 is less

than or equal to 12.5 ps the electrical compliance test passes and is complete for this lane.

Note: An alternate mechanism may be used to get to the appropriate TX compliance state.

2.3 Add-in Card Transmitter Preset Test

This test is run on all card electromechanical form factor Add-in Cards that operate at 8.0 GT/s

and 16.0 GT/s. The test verifies that the Add-in Card produces the correct transmitter

equalization values for each preset in the set of 11 presets.

2.3.1 Starting Configuration

This test is run with devices in the polling.compliance state. This state must be supported to run

the test.

2.3.2 Add-in Card Transmitter Preset Test for 8.0 GT/s

1. Insert the Add-in Card under test into a CBB revision 3.0 or 4.0 without power.

2. Make sure that the compliance toggle outputs (SMP connectors J5 and J85) on the CBB main

board are connected to receive lane zero (SMP connectors J18 and J2) on the CBB riser card

via appropriate SMP to SMP cables.

3. Terminate all Tx Lanes with 50-ohm terminations except the lane under test.

4. Connect the Tx lane under test to a high-speed oscilloscope or equivalent data capture

instrument via SMP to SMA adaptors and phase matched, low loss SMA cables or phase

matched, low loss SMP to SMA cables.

5. Power on the CBB

6. Set Add-in Card to the initial 8.0 GT/s test state using the compliance toggle button on the

CBB.

Note: An alternate mechanism may be used to get to the appropriate TX compliance state.

Test Descriptions

PCI Express Architecture PHY Test Specification | 13

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7. Capture 1.6 million unit-intervals of data (1.6 X 10

X 125.0ps = 200.0µs). Save the captured

waveform to a file with a unique name to identify which preset was enabled when the

waveform was captured. The captured data pattern should be compliance pattern and must

contain runs of 64 ones and 64 zeros.

8. Press the compliance toggle button to cause the card under test to change to the next

transmitter equalization preset value.

9. Repeat steps seven and eight until all 11 presets have been captured and saved.

Note: The waveforms from test 2.1.2 can be used allowing steps one through nine to be

skipped.

10. Use the SigTest Transmitter Preset Test option to read the saved waveform files and

compute the preset values from these. All preset values must be within their specified limits.

2.3.3 Add-in Card Transmitter Preset Test for 16.0 GT/ s

1. Insert the Add-in Card under test into a CBB revision 3.0 or 4.0 without power.

Note: The Variable ISI board from the revision 4.0 test fixtures must not be used for this

test.

2. Make sure that the compliance toggle outputs (SMP connectors J5 and J85) on the CBB main

board are connected to receive lane zero (SMP connectors J18 and J2) on the CBB riser card

via appropriate SMP to SMP cables.

3. Terminate all Tx lanes with 50-ohm terminations except the lane under test.

4. Connect the Tx lane under test to a high-speed oscilloscope or equivalent data capture

instrument via SMP to SMA adaptors and phase matched, low loss SMA cables or phase

matched, low loss SMP to SMA cables.

5. Power on the CBB

6. Set Add-in Card to the initial 16.0 GT/s test state using the compliance toggle button on the

CBB.

Note: An alternate mechanism may be used to get to the appropriate TX compliance state.

7. Capture 2.0 million unit-intervals of data (2.0 X 10

X 62.5ps = 125.0µs). Save the captured

waveform to a file with a unique name to identify which preset was enabled when the

waveform was captured. The captured data pattern should be compliance pattern and must

contain runs of 64 ones and 64 zeros.

Test Descriptions

PCI Express Architecture PHY Test Specification | 14

Revision 4.0, Version 1.01

April 7, 2020

8. Press the compliance toggle button to cause the card under test to change to the next

transmitter equalization preset value.

9. Repeat steps seven and eight until all 11 presets have been captured and saved.

10. Use the SigTest Transmitter Preset Test option to read the saved waveform files and

compute the preset values from these. All preset values must be within their specified limits.

2.4 Add-in Card Transmitter Initial TX EQ Test

This test is run on all card electromechanical form factor Add-in Cards that operate at 8.0 GT/s

and 16.0 GT/s. The test verifies that the Add-in Card will start with the correct TX EQ preset

requested through the protocol.

2.4.1 Starting Configuration

A protocol aware signal source and receiver such as a Protocol Test Card (PTC), Bit Error Ratio

Tester (BERT), other specialized test equipment or any combination of different test equipment

that can perform the test is connected to the device under test via a CBB. Since it is necessary to

send commands to the DUT to adjust the transmitter equalization values and to get the DUT into

loopback mode in order to perform this test, the test equipment must be able to perform the

sequence of steps outlined in the PCI Express Base Specification, Rev. 4.0, sections 4.2.6.4.2 and

in this document’s Appendix A: Getting into Loopback for 8GT/s & 16GT/s.

2.4.2 Add-in Card Transmitter Initial TX EQ test for 8.0 GT/s

Note: For this test no stress is applied from the BERT.

1. Insert the Add-in Card under test into a CBB revision 3.0 or 4.0 without power.

2. Connect the transmitter output of the protocol aware test equipment to the Rx SMP

connectors on the CBB lane under test via SMP to SMA adaptors and phase matched, low

loss SMA cables or phase matched, low loss SMP to SMA cables.

3. Connect the 100 MHz reference clock output from the test equipment to the clock input

SMP connectors on the CBB.

4. Tx lanes other than the lane under test should be unterminated.

5. Connect the Tx lane under test to signal splitters with one set of outputs going to the

receiver inputs of the protocol aware test equipment and the other set of outputs going to a

high-speed oscilloscope or equivalent data capture instrument. All connections to the CBB

should be made via SMP to SMA adaptors and phase matched, low loss SMA cables or phase

matched, low loss SMP to SMA cables. All other connections should be made via phase

matched, low loss SMA cables.

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"PCIe 4.0协议文档：PHY测试规范及PCIe标准"

PCIe 协议标准

PCI 4.0 官方文件

PCI_Express_Base_4.0 PCIE 4.0 Specification 1.0 正式版文档

pcie4.0spec

PCIe4.0_5.0官方协议.zip

PCIE 4.0规范（包括Base和CEM）

PCIe_3.0_spec_pcie3.0spec_pciespec_pcie_PCIe_3.0_spec_pcie3spec_

pg239-pcie-phy

pcie_phy(公开).pdf

pg239-pcie-phy.pdf

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