【免费】PCIe4.0PHYtestspecPCIe4.0协议文档PCIe标准协议_PCIe4.0PHYtestspecPCIe4.0

需积分: 0 52 浏览量更新于2024-01-28 评论 1 收藏 1.91MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

Test Descriptions

PCI Express Architecture PHY Test Specification | 12

Revision 4.0, Version 1.01

April 7, 2020

9. Measure Uncorrelated PWJ Tj @ E-12 using the SigTest analysis program with the 16 GT/s

Pulse Width Jitter template file (PCIE_4_0_CARD\ PCIe_4_16GB_Tx_PWJ.dat).

Note: This measurement is performed with a 16 GT/s toggle (1010) pattern. The

-12 dB behavioral CTLE is applied to the waveform as indicated in the PCI Express Card

Electromechanical Specification. Applying the CTLE is more representative of the signal

present at the Rx latch.

10. If the SigTest analysis program indicates the Add-in Cards Uncorrelated PWJ Tj @ E-12 is less

than or equal to 12.5 ps the electrical compliance test passes and is complete for this lane.

Note: An alternate mechanism may be used to get to the appropriate TX compliance state.

2.3 Add-in Card Transmitter Preset Test

This test is run on all card electromechanical form factor Add-in Cards that operate at 8.0 GT/s

and 16.0 GT/s. The test verifies that the Add-in Card produces the correct transmitter

equalization values for each preset in the set of 11 presets.

2.3.1 Starting Configuration

This test is run with devices in the polling.compliance state. This state must be supported to run

the test.

2.3.2 Add-in Card Transmitter Preset Test for 8.0 GT/s

1. Insert the Add-in Card under test into a CBB revision 3.0 or 4.0 without power.

2. Make sure that the compliance toggle outputs (SMP connectors J5 and J85) on the CBB main

board are connected to receive lane zero (SMP connectors J18 and J2) on the CBB riser card

via appropriate SMP to SMP cables.

3. Terminate all Tx Lanes with 50-ohm terminations except the lane under test.

4. Connect the Tx lane under test to a high-speed oscilloscope or equivalent data capture

instrument via SMP to SMA adaptors and phase matched, low loss SMA cables or phase

matched, low loss SMP to SMA cables.

5. Power on the CBB

6. Set Add-in Card to the initial 8.0 GT/s test state using the compliance toggle button on the

CBB.

Note: An alternate mechanism may be used to get to the appropriate TX compliance state.

Test Descriptions

PCI Express Architecture PHY Test Specification | 13

Revision 4.0, Version 1.01

April 7, 2020

7. Capture 1.6 million unit-intervals of data (1.6 X 10

X 125.0ps = 200.0µs). Save the captured

waveform to a file with a unique name to identify which preset was enabled when the

waveform was captured. The captured data pattern should be compliance pattern and must

contain runs of 64 ones and 64 zeros.

8. Press the compliance toggle button to cause the card under test to change to the next

transmitter equalization preset value.

9. Repeat steps seven and eight until all 11 presets have been captured and saved.

Note: The waveforms from test 2.1.2 can be used allowing steps one through nine to be

skipped.

10. Use the SigTest Transmitter Preset Test option to read the saved waveform files and

compute the preset values from these. All preset values must be within their specified limits.

2.3.3 Add-in Card Transmitter Preset Test for 16.0 GT/ s

1. Insert the Add-in Card under test into a CBB revision 3.0 or 4.0 without power.

Note: The Variable ISI board from the revision 4.0 test fixtures must not be used for this

test.

2. Make sure that the compliance toggle outputs (SMP connectors J5 and J85) on the CBB main

board are connected to receive lane zero (SMP connectors J18 and J2) on the CBB riser card

via appropriate SMP to SMP cables.

3. Terminate all Tx lanes with 50-ohm terminations except the lane under test.

4. Connect the Tx lane under test to a high-speed oscilloscope or equivalent data capture

instrument via SMP to SMA adaptors and phase matched, low loss SMA cables or phase

matched, low loss SMP to SMA cables.

5. Power on the CBB

6. Set Add-in Card to the initial 16.0 GT/s test state using the compliance toggle button on the

CBB.

Note: An alternate mechanism may be used to get to the appropriate TX compliance state.

7. Capture 2.0 million unit-intervals of data (2.0 X 10

X 62.5ps = 125.0µs). Save the captured

waveform to a file with a unique name to identify which preset was enabled when the

waveform was captured. The captured data pattern should be compliance pattern and must

contain runs of 64 ones and 64 zeros.

Test Descriptions

PCI Express Architecture PHY Test Specification | 14

Revision 4.0, Version 1.01

April 7, 2020

8. Press the compliance toggle button to cause the card under test to change to the next

transmitter equalization preset value.

9. Repeat steps seven and eight until all 11 presets have been captured and saved.

10. Use the SigTest Transmitter Preset Test option to read the saved waveform files and

compute the preset values from these. All preset values must be within their specified limits.

2.4 Add-in Card Transmitter Initial TX EQ Test

This test is run on all card electromechanical form factor Add-in Cards that operate at 8.0 GT/s

and 16.0 GT/s. The test verifies that the Add-in Card will start with the correct TX EQ preset

requested through the protocol.

2.4.1 Starting Configuration

A protocol aware signal source and receiver such as a Protocol Test Card (PTC), Bit Error Ratio

Tester (BERT), other specialized test equipment or any combination of different test equipment

that can perform the test is connected to the device under test via a CBB. Since it is necessary to

send commands to the DUT to adjust the transmitter equalization values and to get the DUT into

loopback mode in order to perform this test, the test equipment must be able to perform the

sequence of steps outlined in the PCI Express Base Specification, Rev. 4.0, sections 4.2.6.4.2 and

in this document’s Appendix A: Getting into Loopback for 8GT/s & 16GT/s.

2.4.2 Add-in Card Transmitter Initial TX EQ test for 8.0 GT/s

Note: For this test no stress is applied from the BERT.

1. Insert the Add-in Card under test into a CBB revision 3.0 or 4.0 without power.

2. Connect the transmitter output of the protocol aware test equipment to the Rx SMP

connectors on the CBB lane under test via SMP to SMA adaptors and phase matched, low

loss SMA cables or phase matched, low loss SMP to SMA cables.

3. Connect the 100 MHz reference clock output from the test equipment to the clock input

SMP connectors on the CBB.

4. Tx lanes other than the lane under test should be unterminated.

5. Connect the Tx lane under test to signal splitters with one set of outputs going to the

receiver inputs of the protocol aware test equipment and the other set of outputs going to a

high-speed oscilloscope or equivalent data capture instrument. All connections to the CBB

should be made via SMP to SMA adaptors and phase matched, low loss SMA cables or phase

matched, low loss SMP to SMA cables. All other connections should be made via phase

matched, low loss SMA cables.

剩余66页未读，继续阅读

oLiuShuiWuQing

粉丝: 0
资源: 1

会员权益专享

"PCIe 4.0协议文档：PHY测试规范及PCIe标准"

评论0

会员权益专享

最新资源

"PCIe 4.0协议文档：PHY测试规范及PCIe标准"

评论0

PCIe协议规范合集，包括PCI-Express-Base/CEM/PHY TEST等2.0-6.0

PCI Express Architecture PHY Test Specification

DFI ddr phy interface 4.0最新文档

pcie3.0 phy手册

pcie_3_0_phy_test_spec_ve

hi3531d pcie phy

/ { model = "Rockchip RK3568 NVR DEMO DDR4 V10 ANDROID Board"; compatible = "rockchip,rk3568-nvr-demo-ddr4-v10", "rockchip,rk3568"; }; &pcie30phy { status = "disabled"; }; &pcie3x1 { status = "disabled"; }; &pcie3x2 { status = "disabled"; };每一行代码解释

pcie phy 开源项目

pcie phy pipe

ddr dfi 4.0协议

pcie gen5 spec

mipi c-phy v2.1协议文档

openwrt mt7620a PCIE 驱动程序详细分析

phy芯片的不同接口

mipi d phy spec

mipi m-phy spec下载

pci express architecture phy test specification revision2.0

pcie控制器的phy是什么，怎么用

mipi dphy协议文档

mipi d_phy spec

会员权益专享

最新资源