TI TLC1549系列10位A/D转换器特性介绍

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TLC1549系列是TI公司推出的一款10位分辨率的模拟到数字(A/D)转换器，它属于开关电容式、逐次逼近型设计，特别适合在串行接口环境中工作。该系列包括TLC1549C、TLC1549I和TLC1549M三种型号，它们都具备自动采样保持功能，能有效抑制噪声对模拟电路的影响。这些A/D转换器的核心特性包括： 1. **高分辨率**：TLC1549系列提供了10位的模拟输入精度，这意味着它可以提供非常细腻的数字输出，适用于对信号精确度要求较高的应用。 2. **内置采样保持**：无需额外硬件支持，内部采样保持电路确保在转换期间保持输入信号稳定，减少转换误差。 3. **总未校正误差**：最大误差范围为±1LSB（Least Significant Bit，最低有效位），这意味着转换结果具有良好的线性准确度。 4. **集成系统时钟**：设备内部集成了时钟源，减少了对外部时钟的需求，简化了系统设计。 5. **三线接口**：通过三个状态的输出引脚（芯片选择CS、输入输出时钟I/O CLOCK和数据输出DATA OUT），这些转换器可以与主机处理器的串行端口实现简单连接，便于系统集成。 6. **兼容性**：TLC1549系列与TLC549和TLV1549等其他设备终端兼容，方便用户在现有系统中替换或升级。 7. **CMOS技术**：采用CMOS工艺制造，使得转换器功耗低，适合电池供电或者电源效率高的应用。 8. **宽温工作范围**：由于采用了开关电容设计，TLC1549C能够在整个操作温度范围内保持低误差的转换，适应恶劣环境下的稳定性能。 9. **噪声隔离**：差分高阻抗参考输入允许进行比率测量、信号缩放以及逻辑和供电噪声的隔离，提高系统信号处理能力。 TLC1549系列是高效、精确且易于集成的A/D转换解决方案，广泛应用于需要高精度、低噪声和简化接口设计的工业控制、通信、仪表和信号处理等领域。

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

Table 1. Mode Operation

MODES CS

NO. OF

I/O CLOCKS

MSB AT Terminal 6

†

TIMING

DIAGRAM

Mode 1 High between conversion cycles 10 CS falling edge Figure 6

Fast Modes

Mode 2 Low continuously 10 Within 21 µs Figure 7

Fast

Modes

Mode 3 High between conversion cycles 11 to 16

‡

CS falling edge Figure 8

Mode 4 Low continuously 16

‡

Within 21 µs Figure 9

Slow Modes

Mode 5 High between conversion cycles 11 to 16

‡

CS falling edge Figure 10

Slo

Modes

Mode 6 Low continuously 16

‡

16th clock falling edge Figure 11

†

This timing also initiates serial interface communication.

‡

No more than 16 clocks should be used.

All the modes require a minimum period of 21 µs after the falling edge of the tenth I/O CLOCK before a new

transfer sequence can begin. During a serial I/O CLOCK data transfer, CS

must be active (low) so that I/O

CLOCK is enabled. When CS

is toggled between data transfers (modes 1, 3, and 5), the transitions at CS are

recognized as valid only if the level is maintained for a minimum period of 1.425 µs after the transition. If the

transfer is more than ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur within

9.5 µs after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with the

host serial interface and CS

has to be toggled to restore proper operation.

fast modes

The TLC1549 is in a fast mode when the serial I/O CLOCK data transfer is completed within 21 µs from the falling

edge of the tenth I/O CLOCK. With a ten-clock serial transfer, the device can only run in a fast mode.

mode 1: fast mode, CS inactive (high) between transfers, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The

falling edge of CS

begins the sequence by removing DATA OUT from the high-impedance state. The rising edge

of CS

ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.

Also, the rising edge of CS

disables I/O CLOCK within a setup time plus two falling edges of the internal system

clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After

the initial conversion cycle, CS

is held active (low) for subsequent conversions. Within 21 µs after the falling

edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

mode 3: fast mode, CS inactive (high) between transfers, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS

begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS

ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS

disables I/O CLOCK within a setup time plus two falling edges of the

internal system clock.

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS

is held active (low) for subsequent conversions. Within 21 µs after

the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

slow modes

In a slow mode, the serial I/O CLOCK data transfer is completed after 21 µs from the falling edge of the tenth

I/O CLOCK.

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