xvi Preface
In the previous chapter, designs for combinational and sequential circuits were
dealt. Test benches for the same are presented in this chapter. Usually, the test
bench size will be smaller than that of the design. This chapter is especially useful
for verification engineers.
Chapter 5 deals with the Register Transfer Level Coding Guidelines. Every de-
signer is vitally interested in making his or her design work when implemented as
a hardware, which uses FPGA or ASIC. For successful working of a system, RTL
coding techniques are inevitable. This requires a high degree of discipline or care
while designing such systems. This chapter discusses RTL coding techniques in
depth, which is basically adhering to synchronous design practices. RTL approach
deals with the regulation of data flow, and how the data is processed using register
transfer level as the primary means. Since we deal with a synchronous design, it
should naturally run smoothly through various tools such as simulation, synthesis,
and place and route, which tools are described at length in succeeding chapters.
Chapter 6 presents the VLSI Design flow along with the design methodologies
that may be gainfully employed so that one may become conversant with various
steps involved in designing a product. Several designs were considered in Chapter
3 and their test benches in Chapter 4. This was followed by RTL coding guide-
lines in Chapter 5. The next logical step in the design flow is the simulation, vital
for testing one’s design. All the Verilog designs presented in the third chapter are
analyzed using waveforms in the present chapter. Industry standard Modelsim tool
of Mentor Graphics is employed for the simulation. A command summary of the
Modelsim tool, which serves as a quick reference while using the tool, is also fur-
nished. Even though the functionality of a design is checked using simulation, it
does not test time critical paths or furnish insights into gate delays, unless back
annotated, since simulation does not map a target chip such as an FPGA, where
the design will have to reside ultimately. These features are possible with synthe-
sis tool, which is presented in the next chapter.
Chapter 7 covers the synthesis of designs using Synplify tool, widely used in
industries. The salient features of synthesis are mapping of an FPGA device, logic
optimization, and viewing schematic circuit diagrams of the Verilog code. The
tool creates optimized Verilog file and Electronic Data Information Format
(EDIF) file, which may be used for simulation and vendor specific place and route
respectively. EDIF file is exported to the next tool, the Place and Route tool, for
creating a bit stream of the design. Synplify tool supports all types of FPGAs. In
order to learn and fix compilation errors and simulation errors in Modelsim and
Synplify tools, errors are created deliberately and known correction applied. A
command summary of the Synplify tool is furnished for quick reference while us-
ing the tool.
Chapter 8 covers the Place and Route (P&R) tool of Xilinx, also widely used in
industries. The salient features of Xilinx P&R are the creation of a ‘bit’ file from
EDIF file created by the Synplify tool or from source file directly, specification of
user constraints such as clock speed and FPGA pins, remapping of the target
FPGA device if desired, back annotation and floor planning. The back annotated
file, which reflects the actual gate delays, is simulated again in Modelsim to en-
sure that the design is working correctly at the maximum frequency reported by
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