A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
00: 66 MHZ (1:1)
AD29: STRAP SET SELECTION
00: SHORT, NON-S2K INTERFACE
PCI_CBE#0 : EXTERNAL SIP ROM ENABLE
11: FARTHEST S2K INTERFACE, DUAL CPU
AD[31..30] : CLK SPEED
DEFAULT
0: USE FULL STRAPPING SET
10: FAR S2K INTERFACE, DUAL CPU
0: DISABLE
10: SLOT1 INTERFACE (MOBILE)
01: SINGLE S2K INTERFACE, CLOSE
DEFAULT
1: USE REDUCED STRAPPING SET
01: 100 MHZ (1.5:1)
1: ENABLE
DEFAULT
AD[15..14] :S2K/SLOT1 SELECT & CALIBRATION
AD24: INCLK_DELAY_ENABLE
00: S2K INTERFACE (MOBILE)
DEFAULT
1: ENABLE
DEFAULT
DEFAULT
10: 166MHZ (2.5:1)
0: DISABLE
AD[27..26] : CPU S2K BUS LENGTH
11: 133 MHZ (2:1)
1: ENABLE
0: DISABLE
AD28: SPREAD SPECTRUM ENABLE
DEFAULT
1: ???
0: ???
AD25: RESERVED
DEFAULT
DEFAULT
AD[23..21] : SKEW ADJUST
000: ??? DETERMINE DURING
BRING-UP & FIX FOR
PRODUCTION
0: ???
1: ???
DEFAULT
1: ENABLEDEFAULT
0: DISABLE
AD8: ENABLE K7 OUTCLK DELAY
DEFAULT 1: ENABLE
AD11 : INTERAL CLOCK GENERATOR
0: DISABLE
AD[12] : FLAT PANEL ID MSB
ID4
AD[7..4] : FLAT PANEL ID
AD[10..9] : RESERVED[4..3]
1: 66MHz
AD3: PCI66 MODE
0: 33MHzDEFAULT
1: ENABLE
AD2: CAL DEFAULTS FOR CPU
0: DISABLEDEFAULT
AD0 : INTERAL GRAPHICS ENABLE
1: USE INTERNAL BY DEFAULT
DEFAULT 0: IF NO EXTERNAL, USE INTERNAL
DEFAULT
1: ???
0: ???
DEFAULT
1: ???
0: ???
1: ???
0: ???DEFAULT
AD1: RESERVED
DEFAULT
AD20: PCICLK EXPANSION
0: REQ/GNT3 USED AS REQ/GNT
1: REQ/GNT3 USED AS PCICLKS
01: S2K INTERFACE (DESKTOP)
11: SLOT1 INTERFACE (DESKTOP)
AD13: RESERVED
DEFAULT
PCI_CBE#3 : PRODUCTION TEST
1: NORMAL OPERATION
0: SHORT TIMERS FOR PROD TEST
DEBUG MODE ONLY
1: ENABLE
0: DISABLE
PCI_ACT_REQ# : INTERNAL CLOCK GENERATOR(A21 ASIC)
DEFAULT
ATI 5/27
ATI 6/19
LA-1481 M/B
0.2
ATI MOBILITY U1_STRAP INPUT
10 47
!"#
,
$%
14, 2002
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
AD4
AD5
AD7
AD6
AD[0..31]
CBE#0
AD0AD20
AD14
AD8
AD22
AD24
AD9
AD28
AD1
AD26
AD21
AD3
AD29
AD11
AD2
AD23
AD10
AD15
AD13
AD25
AD30
AD12
AD27
CBE#3
PCI_ACT_REQ#
AD31
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
R175 4.7K_0603
R429 @10K_0603
R155 4.7K_0603
R194 @4.7K_0603
R70 @4.7K_0603
R435 @10K_0603
R174 @10K_0603
R167 4.7K_0603
R432 4.7K_0603
R46 10K_0603
R430 4.7K_0603
R166 @10K_0603
R433 @10K_0603
R431 @10K_0603
R440 4.7K_0603
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R437 @10K_0603
R37 5.6K_0603
1 2
R427 2.2K_0603
R40 10K_0603
1 2
R64 @4.7K_0603
1 2
R39 @10K_0603
1 2
R63 4.7K_0603
1 2
R62 4.7K_0603
1 2
R38 @10K_0603
1 2
R66 4.7K_0603
1 2
R428 @10K_0603
R42 @10K_0603
1 2
R67 4.7K_0603
1 2
R43 @10K_0603
1 2
R41 @10K_0603
1 2
R65 4.7K_0603
1 2
R45 10K_0603
1 2
R69 @4.7K_0603
1 2
R44 @10K_0603
1 2
R68 4.7K_0603
1 2
R61 3.3K_0603
1 2
R47 @10K_0603
1 2
R71 4.7K_0603
1 2
R48 @10K_0603
1 2
R72 4.7K_0603
1 2
R49 @10K_0603
1 2
R73 4.7K_0603
1 2
R160 @10K_0603
1 2
R161 4.7K_0603
1 2
R147 @10K_0603
1 2
R148 4.7K_0603
1 2
R183 @10K_0603
R102 10K_0603
1 2
R154 @10K_0603
R103 10K_0603
1 2
R438 4.7K_0603
R117 10K_0603
1 2
R184 4.7K_0603
R118 10K_0603
1 2
R439 @10K_0603
R434 4.7K_0603
Q6
@2N7002
2
13
R436 4.7K_0603
R193 10K_0603
AD[0..31]8,16,20,21,22,25,32
PID3 15,28
PID2 15,28
PID1 15,28
PID0 15,28
CBE#08,16,20,21,22,25
CBE#38,16,20,21,22,25
PCI_ACT_REQ#8,17
FSB_100/133#4,13