![](https://csdnimg.cn/release/download_crawler_static/11905489/bg12.jpg)
Table 11. IP Core Installation Locations
Location Software Platform
<drive>:\intelFPGA_pro\quartus\ip\altera
Intel Quartus Prime Pro Edition Windows*
<drive>:\intelFPGA\quartus\ip\altera
Intel Quartus Prime Standard
Edition
Windows
<home directory>:/intelFPGA_pro/quartus/ip/altera
Intel Quartus Prime Pro Edition Linux*
<home directory>:/intelFPGA/quartus/ip/altera
Intel Quartus Prime Standard
Edition
Linux
2.1.1. Intel FPGA IP Evaluation Mode
The free Intel FPGA IP Evaluation Mode allows you to evaluate licensed Intel FPGA IP
cores in simulation and hardware before purchase. Intel FPGA IP Evaluation Mode
supports the following evaluations without additional license:
• Simulate the behavior of a licensed Intel FPGA IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
Intel FPGA IP Evaluation Mode supports the following operation modes:
• Tethered—Allows running the design containing the licensed Intel FPGA IP
indefinitely with a connection between your board and the host computer.
Tethered mode requires a serial joint test action group (JTAG) cable connected
between the JTAG port on your board and the host computer, which is running the
Intel Quartus Prime Programmer for the duration of the hardware evaluation
period. The Programmer only requires a minimum installation of the Intel Quartus
Prime software, and requires no Intel Quartus Prime license. The host computer
controls the evaluation time by sending a periodic signal to the device via the
JTAG port. If all licensed IP cores in the design support tethered mode, the
evaluation time runs until any IP core evaluation expires. If all of the IP cores
support unlimited evaluation time, the device does not time-out.
• Untethered—Allows running the design containing the licensed IP for a limited
time. The IP core reverts to untethered mode if the device disconnects from the
host computer running the Intel Quartus Prime software. The IP core also reverts
to untethered mode if any other licensed IP core in the design does not support
tethered mode.
When the evaluation time expires for any licensed Intel FPGA IP in the design, the
design stops functioning. All IP cores that use the Intel FPGA IP Evaluation Mode time
out simultaneously when any IP core in the design times out. When the evaluation
time expires, you must reprogram the FPGA device before continuing hardware
verification. To extend use of the IP core for production, purchase a full production
license for the IP core.
You must purchase the license and generate a full production license key before you
can generate an unrestricted device programming file. During Intel FPGA IP Evaluation
Mode, the Compiler only generates a time-limited device programming file (<project
name>_time_limited.sof) that expires at the time limit.
2. Getting Started
UG-20078 | 2018.08.09
RapidIO Intel FPGA IP User Guide
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