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首页E6500内核手册:飞思卡尔(恩智浦)T2系列处理器开发必备
E6500内核手册:飞思卡尔(恩智浦)T2系列处理器开发必备
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"POWERPC E6500内核是飞思卡尔(现为恩智浦半导体)T2系列处理器的核心组件,其数据手册详细介绍了该架构的特性与功能。E6500 Core Reference Manual提供了关于这个高性能处理器内核的全面指南,包括设计和开发的相关信息。文档版本为Rev0,发布日期为2014年6月。"
在POWERPC E6500的架构中,我们可以挖掘到以下几个关键知识点:
1. **Power Architecture**: E6500内核基于Power Architecture,这是一个开放的指令集架构(ISA),由IBM、Motorola和Apple共同创建,并由Power.org进行商标授权。它被广泛应用于高性能计算、服务器、嵌入式系统和通信设备等领域。
2. **E6500 Core**: E6500是飞思卡尔(现恩智浦)推出的一款高性能处理器核心,适用于需要高效能计算能力的应用,如网络、通信和嵌入式系统。
3. **核心技术特性**:
- **AltiVec**: AltiVec技术是一种向量处理单元(Vector Processing Unit,VPU),提供并行计算能力,提高了处理多媒体和浮点运算的效率。
- **Energy Efficient Solutions**: E6500内核可能集成了能源效率优化方案,以减少功耗并提高运行时的能效。
- **Processor Expert**: 这是飞思卡尔的一个工具,用于自动生成和配置微控制器的软件组件,简化了软件开发流程。
- **QorIVa, QorIQ**: QorIVa和QorIQ是飞思卡尔的处理器家族,可能与E6500内核相关的多核解决方案,提供可扩展性和高性能。
4. **知识产权与法律条款**:文档明确指出,提供的信息仅用于帮助系统和软件实施者使用Freescale产品。它不包含任何设计或制造集成电路的版权许可,这意味着用户不能直接复制内核设计,但可以基于信息开发兼容的产品。
5. **开发工具与支持**:Freescale的工具如CodeWarrior、Processor Expert和C-Ware等可能为E6500的开发提供了全面的开发环境和库支持。
6. **商标与品牌**:文档中列举了一系列飞思卡尔的商标,如ColdFire、Kinetis、PowerQUICC等,这些品牌可能代表了与E6500内核相关的其他处理器系列或技术。
7. **技术规格**:虽然具体的技术规格未在摘要中列出,但完整的数据手册会包含如时钟速度、内存接口、I/O接口、功耗和散热设计等关键参数。
8. **安全与认证**:文档中提到的安全相关商标如SafeAssure可能意味着E6500内核设计考虑了安全性,提供了一定的硬件安全特性。
POWERPC E6500内核是一个高度集成且性能强大的处理器核心,适用于需要高性能和高能效的复杂应用。开发人员可以利用提供的参考手册来理解和开发基于E6500的系统。
e6500 Core Reference Manual, Rev 0
xvi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
9.9 Debug events.................................................................................................................. 9-34
9.9.1 Embedded hypervisor ................................................................................................ 9-35
9.9.2 Internal and external debug modes ............................................................................ 9-35
9.9.3 Changing the debug facility state in internal debug mode......................................... 9-35
9.9.4 IAC, DAC, ICMP, BRT, IRPT, RET, CIRPT, CRET
debug condition response table.............................................................................. 9-36
9.9.5 Instruction address compare debug condition ........................................................... 9-36
9.9.6 Data address compare debug condition ..................................................................... 9-37
9.9.7 Instruction complete debug condition........................................................................ 9-38
9.9.8 Branch taken debug condition ................................................................................... 9-39
9.9.9 Interrupt taken debug condition................................................................................. 9-39
9.9.10 Interrupt return debug condition ................................................................................ 9-40
9.9.11 Critical interrupt taken debug condition .................................................................... 9-40
9.9.12 Critical return debug condition .................................................................................. 9-41
9.9.13 Unconditional debug event condition ........................................................................ 9-41
9.9.14 TRAP debug condition .............................................................................................. 9-42
9.9.15 Debugger Notify Interrupt (DNI) debug condition.................................................... 9-43
9.9.16 Dedicated debug halt request events.......................................................................... 9-44
9.9.16.1 Debug Halt Request (corex_dbg_halt_thrdn) input............................................... 9-45
9.9.16.2 Debugger Notify Halt (dnh) instruction................................................................. 9-45
9.9.16.3 Cross-thread debug halt requests ........................................................................... 9-46
9.9.17 Simultaneous debug event priorities.......................................................................... 9-46
9.9.17.1 Simultaneous debug event handing—events within same owner .......................... 9-47
9.9.17.2 Simultaneous debug event handing—events of different owners .......................... 9-48
9.10 External debug interface ................................................................................................ 9-48
9.10.1 Processor run states.................................................................................................... 9-48
9.10.1.1 Halt ........................................................................................................................ 9-48
9.10.1.1.1 Watchdog timer during debug halted state ........................................................ 9-49
9.10.1.2 Stop (freeze)...........................................................................................................9-49
9.10.1.3 Wait........................................................................................................................ 9-50
9.10.1.4 Thread disabled...................................................................................................... 9-50
9.10.1.5 Entering/exiting processor run states..................................................................... 9-50
9.10.2 Single-step ................................................................................................................. 9-52
9.10.3 Resource access ......................................................................................................... 9-52
9.10.3.1 Memory-mapped access ........................................................................................ 9-52
9.10.3.2 Special-purpose register access (Nexus only) ....................................................... 9-58
9.10.4 Instruction jamming................................................................................................... 9-58
9.10.4.1 Debug storage space (IJCFG[IJMODE] = 1) ........................................................ 9-59
9.10.4.2 Instruction jamming input...................................................................................... 9-61
9.10.4.3 Supported instruction jamming instructions.......................................................... 9-62
9.10.4.4 Instructions supported only during instruction jamming....................................... 9-64
e6500 Core Reference Manual, Rev 0
Freescale Semiconductor xvii
Contents
Paragraph
Number Title
Page
Number
9.10.4.5 Exception conditions and affected architectural registers ..................................... 9-65
9.10.4.6 Instruction jamming status..................................................................................... 9-66
9.10.4.7 Special note on jamming store instructions........................................................... 9-66
9.10.4.8 Instruction jamming output.................................................................................... 9-67
9.10.4.9 IJAM procedure ..................................................................................................... 9-67
9.10.4.9.1 IJAM of instructions with input data ................................................................. 9-67
9.10.4.9.2 IJAM of instructions with output data ............................................................... 9-68
9.10.4.9.3 IJAM of instructions with no associated data.................................................... 9-68
9.10.4.9.4 IJAM of instructions to read or write SPRs, PMRs, CR, FPSCR, and MSR .... 9-68
9.10.4.10 Instruction jamming error conditions .................................................................... 9-69
9.11 Nexus trace..................................................................................................................... 9-69
9.11.1 Nexus features............................................................................................................9-70
9.11.2 Enabling Nexus operations on the processor ............................................................. 9-71
9.11.3 Modes of operation .................................................................................................... 9-71
9.11.4 Supported TCODEs ................................................................................................... 9-71
9.11.5 Nexus message fields................................................................................................. 9-78
9.11.5.1 TCODE field.......................................................................................................... 9-78
9.11.5.2 Source ID field (SRC)............................................................................................ 9-78
9.11.5.3 Relative Address field (U-ADDR)......................................................................... 9-79
9.11.5.4 Full Address field (F-ADDR)................................................................................ 9-79
9.11.5.5 Timestamp field (TSTAMP) .................................................................................. 9-79
9.11.6 Nexus message queues............................................................................................... 9-80
9.11.6.1 Message queue overrun ......................................................................................... 9-81
9.11.6.2 CPU stall ................................................................................................................ 9-81
9.11.6.3 Message suppression ............................................................................................. 9-81
9.11.7 Nexus message priority.............................................................................................. 9-81
9.11.7.1 Data Acquisition Message priority loss response and retry................................... 9-82
9.11.7.2 Ownership Trace message priority loss response and retry................................... 9-82
9.11.7.3 Program Trace Message priority loss response and retry ...................................... 9-83
9.11.8 Timestamp Correlation Message priority loss response and retry............................. 9-83
9.11.9 Performance Profile Message priority loss response and retry.................................. 9-83
9.11.10 Data Trace Message priority loss response and retry ................................................ 9-83
9.11.11 Debug Status messages .............................................................................................. 9-83
9.11.12 Error messages...........................................................................................................9-83
9.11.13 Resource full messages.............................................................................................. 9-84
9.11.14 Program Trace............................................................................................................9-84
9.11.14.1 Program Trace—enable and disable ...................................................................... 9-85
9.11.14.2 Lite Program Trace mode ...................................................................................... 9-86
9.11.14.2.1 Lite Program Trace mode—enabling ................................................................ 9-86
9.11.14.2.2 Lite Program Trace mode—how it works ......................................................... 9-86
9.11.14.2.3 Lite Program Trace mode—example................................................................. 9-88
e6500 Core Reference Manual, Rev 0
xviii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
9.11.14.3 Sequential instruction count field .......................................................................... 9-89
9.11.14.4 Branch/predicate history events ............................................................................. 9-89
9.11.14.5 Indirect Branch message events............................................................................. 9-90
9.11.14.6 Resource Full events.............................................................................................. 9-90
9.11.14.7 Program Correlation events ................................................................................... 9-90
9.11.14.8 Synchronization conditions ................................................................................... 9-91
9.11.15 Data Trace .................................................................................................................. 9-92
9.11.15.1 Data Trace—enable and disable ............................................................................ 9-92
9.11.15.2 Data Trace range control........................................................................................ 9-93
9.11.15.3 Data Trace Size (DSZ) field .................................................................................. 9-94
9.11.15.4 Data Trace address field......................................................................................... 9-94
9.11.15.5 Data Trace data field.............................................................................................. 9-95
9.11.15.6 Data Trace message events .................................................................................... 9-95
9.11.16 Ownership Trace........................................................................................................ 9-95
9.11.16.1 Ownership Trace—enable and disable .................................................................. 9-95
9.11.16.2 Ownership Trace Process field .............................................................................. 9-96
9.11.16.3 Standard Ownership Trace message events........................................................... 9-96
9.11.16.4 “Sync” Ownership Trace message events.............................................................. 9-97
9.11.17 Data Acquisition Trace .............................................................................................. 9-97
9.11.17.1 Data Acquisition Trace—enable and disable......................................................... 9-97
9.11.17.2 Data Acquisition ID Tag field................................................................................ 9-98
9.11.17.3 Data Acquisition Data field ................................................................................... 9-98
9.11.17.4 Data Acquisition Trace event................................................................................. 9-98
9.11.18 Watchpoint Trace ....................................................................................................... 9-98
9.11.18.1 Watchpoint events.................................................................................................. 9-98
9.11.18.2 Watchpoint Trace—enable and disable ............................................................... 9-100
9.11.18.3 Watchpoint Hit field............................................................................................. 9-100
9.11.18.4 Watchpoint Trace message events ....................................................................... 9-101
9.11.19 Timestamp Correlation messages ............................................................................ 9-101
9.11.20 Performance Profile messages ................................................................................. 9-101
9.11.20.1 Performance Profile messages—enable and disable ........................................... 9-101
9.11.20.2 Performance Profile message events ................................................................... 9-102
9.11.20.3 Performance Profile message configuration ........................................................ 9-102
9.11.20.4 Performance Profile Sync field............................................................................ 9-102
9.12 Performance monitor ................................................................................................... 9-102
9.12.1 Overview.................................................................................................................. 9-103
9.12.2 Performance monitor instructions............................................................................ 9-105
9.12.3 Performance monitor interrupt................................................................................. 9-105
9.12.4 Event counting ......................................................................................................... 9-106
9.12.4.1 Processor context configurability ........................................................................ 9-106
9.12.4.2 Processor performance monitor and program counter capture function ............. 9-107
e6500 Core Reference Manual, Rev 0
Freescale Semiconductor xix
Contents
Paragraph
Number Title
Page
Number
9.12.5 Examples.................................................................................................................. 9-108
9.12.5.1 Chaining counters ................................................................................................ 9-108
9.12.6 Event selection ......................................................................................................... 9-109
Chapter 10
Execution Timing
10.1 Terminology and conventions........................................................................................ 10-1
10.2 Instruction timing overview ........................................................................................... 10-3
10.3 General timing considerations ....................................................................................... 10-6
10.3.1 General instruction flow ............................................................................................ 10-7
10.3.2 Instruction fetch timing considerations...................................................................... 10-8
10.3.2.1 L1 and L2 TLB access times ................................................................................. 10-8
10.3.2.2 Interrupts associated with instruction fetching ...................................................... 10-9
10.3.2.3 Cache-related latency............................................................................................. 10-9
10.3.3 Dispatch, issue, and completion considerations ...................................................... 10-10
10.3.3.1 Instruction serialization ....................................................................................... 10-11
10.3.4 Memory synchronization timing considerations...................................................... 10-12
10.3.4.1 sync instruction timing considerations ................................................................ 10-12
10.3.4.2 mbar instruction timing considerations .............................................................. 10-13
10.4 Execution ..................................................................................................................... 10-13
10.4.1 Branch execution unit .............................................................................................. 10-14
10.4.1.1 Branch instructions and completion .................................................................... 10-14
10.4.1.2 Branch prediction and resolution......................................................................... 10-15
10.4.1.2.1 Branch predictor structure and operation ........................................................ 10-16
10.4.1.2.2 Global History (GHR) register and Pattern History Table (PHT) ................... 10-17
10.4.1.2.3 Segment Target Address Cache (STAC), Segment Target Index
Cache (STIC), and link stack....................................................................... 10-17
10.4.1.2.4 Branch predictor operations controlled by BUCSR ........................................ 10-18
10.4.1.2.5 Branch prediction special cases: multiple matches and phantom branches .... 10-19
10.4.1.3 Changing LR and CTR in branch instructions .................................................... 10-19
10.4.2 Complex and simple unit execution......................................................................... 10-19
10.4.2.1 CFX divide execution .......................................................................................... 10-20
10.4.2.2 CFX multiply execution....................................................................................... 10-20
10.4.2.3 CFX bypass path.................................................................................................. 10-21
10.4.3 AltiVec (vector) execution ....................................................................................... 10-22
10.4.4 Load/store execution................................................................................................ 10-23
10.4.4.1 Effect of operand placement on performance...................................................... 10-23
10.5 Instruction latency summary........................................................................................ 10-24
10.6 Instruction scheduling guidelines ................................................................................ 10-45
e6500 Core Reference Manual, Rev 0
xx Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Chapter 11
Core and Cluster Software Initialization Requirements
11.1 Core and cluster state and software initialization after reset ......................................... 11-1
11.2 MMU state ..................................................................................................................... 11-1
11.3 Thread state.................................................................................................................... 11-1
11.4 Core register state .......................................................................................................... 11-2
11.4.1 GPRs .......................................................................................................................... 11-2
11.4.2 FPRs........................................................................................................................... 11-2
11.4.3 VRs ............................................................................................................................ 11-3
11.4.4 SPRs........................................................................................................................... 11-3
11.4.5 MSR, FPSCR, and VSCR.......................................................................................... 11-4
11.5 Timer state...................................................................................................................... 11-5
11.6 L1 cache state................................................................................................................. 11-5
11.7 L2 cache state................................................................................................................. 11-6
11.8 Branch target buffer state ............................................................................................... 11-7
Appendix A
Simplified Mnemonics
A.1 Overview......................................................................................................................... A-1
A.2 Subtract simplified mnemonics....................................................................................... A-1
A.2.1 Subtract immediate ..................................................................................................... A-1
A.2.2 Subtract ....................................................................................................................... A-2
A.3 Rotate and shift simplified mnemonics........................................................................... A-2
A.3.1 Operations on words ................................................................................................... A-2
A.3.2 Operations on doublewords ........................................................................................ A-3
A.4 Branch instruction simplified mnemonics ...................................................................... A-4
A.4.1 Key facts about simplified branch mnemonics ........................................................... A-5
A.4.2 Eliminating the BO operand ....................................................................................... A-6
A.4.3 Incorporating the BO branch prediction ..................................................................... A-7
A.4.4 The BI operand—CR bit and field representations .................................................... A-8
A.4.4.1 BI operand instruction encoding............................................................................. A-8
A.4.4.1.1 Specifying a CR bit............................................................................................. A-9
A.4.4.1.2 The crS operand ............................................................................................... A-11
A.4.5 Simplified mnemonics that incorporate the BO operand.......................................... A-11
A.4.5.1 Examples that Eliminate the BO Operand............................................................ A-12
A.4.6 Simplified mnemonics that incorporate CR conditions (eliminate BO
and replace BI with crS)....................................................................................... A-15
A.4.6.1 Branch simplified mnemonics that incorporate CR conditions:
examples ........................................................................................................... A-17
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