Micron MT25QU256ABA Serial NOR Flash: 高速SPI接口与多I/O选项

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"MT25QU256ABA是镁光公司的一款串行NOR闪存芯片，适用于需要高速、高容量数据存储的应用。这款芯片提供了SPI兼容的串行总线接口，支持单传输率（STR）和双传输率（DTR）模式，最大时钟频率可达166MHz（STR）和90MHz（DTR）。通过双通道或四通道I/O命令，可以实现高达90MB/s的数据传输速率，提高了系统的吞吐性能。它支持扩展的、双I/O和四I/O协议，无论是STR还是DTR模式。 MT25QU256ABA的一个关键特性是执行在位（Execute-in-Place, XIP）功能，允许代码直接从闪存中运行，减少了对RAM的需求。该芯片还提供了程序/擦除暂停操作，使得在处理大容量数据时更灵活。此外，它具有易失性和非易失性配置设置，以及软件重置功能。部分型号还配备了一个额外的复位引脚。该芯片提供3字节和4字节地址模式，扩展了内存访问范围，可超过128Mb的界限。还有一个专用的64字节一次性可编程（OTP）区域，该区域可以读取并由用户锁定，通过PROGRAMOTP命令实现永久锁定。MT25QU256ABA具备擦除功能，包括整片擦除、64KB的扇区擦除以及4KB和32KB的子扇区擦除。其擦除速度分别为400KB/s（64KB扇区）和80KB/s（4KB子扇区），程序写入速度达到2MB/s。在安全性方面，MT25QU256ABA提供了针对每个64KB扇区的易失性和非易失性锁定及软件写保护。这些特性确保了数据的安全性和防止未经授权的访问或修改。" 此数据手册详细介绍了镁光MT25QU256ABA串行NOR闪存芯片的技术规格和功能，对于设计使用此类存储解决方案的工程师来说，是重要的参考资料。它涵盖了从接口速度到数据保护的所有关键特性，有助于用户充分理解和有效地利用这款存储设备。

Signal Descriptions

The signal description table below is a comprehensive list of signals for the MT25Q fam-

ily devices. All signals listed may not be supported on this device. See Signal Assign-

ments for information specific to this device.

Table 1: Signal Descriptions

Symbol Type Description

S# Input Chip select: When S# is driven HIGH, the device will enter standby mode, unless an internal

PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress. All other input pins are ig-

nored and the output pins are tri-stated. On parts with the pin configuration offering a dedica-

ted RESET# pin, however, the RESET# input pin remains active even when S# is HIGH.

Driving S# LOW enables the device, placing it in the active mode.

After power-up, a falling edge on S# is required prior to the start of any command.

C Input Clock: Provides the timing of the serial interface. Command inputs are latched on the rising

edge of the clock. In STR commands or protocol, address and data inputs are latched on the

rising edge of the clock, while data is output on the falling edge of the clock. In DTR com-

mands or protocol, address and data inputs are latched on both edges of the clock, and data is

output on both edges of the clock.

RESET# Input RESET#: When RESET# is driven LOW, the device is reset and the outputs are tri-stated. If RE-

SET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, da-

ta may be lost. The RESET# functionality can be disabled using bit 4 of the nonvolatile configu-

ration register or bit 4 of the enhanced volatile configuration register.

For pin configurations that share the DQ3 pin with RESET#, the RESET# functionality is disabled

in QIO-SPI mode.

HOLD# Input HOLD: Pauses serial communications with the device without deselecting or resetting the de-

vice. Outputs are tri-stated and inputs are ignored. The HOLD# functionality can be disabled

using bit 4 of the nonvolatile configuration register or bit 4 of the enhanced volatile configura-

tion register.

For pin configurations that share the DQ3 pin with HOLD#, the HOLD# functionality is disabled

in QIO-SPI mode or when DTR operation is enabled.

W# Input Write protect: Freezes the status register in conjunction with the enable/disable bit of the sta-

tus register. When the enable/disable bit of the status register is set to 1 and the W# signal is

driven LOW, the status register nonvolatile bits become read-only and the WRITE STATUS REG-

ISTER operation will not execute. During the extended-SPI protocol with QOFR and QIOFR in-

structions, and with QIO-SPI protocol, this pin function is an input/output as DQ2 functionality.

This signal does not have internal pull-ups, it cannot be left floating and must be driven, even

if none of W#/DQ2 function is used.

DQ[3:0] I/O Serial I/O: The bidirectional DQ signals transfer address, data, and command information.

When using legacy (x1) SPI commands in extended I/O protocol (XIO-SPI), DQ0 is an input and

DQ1 is an output. DQ[3:2] are not used.

When using dual commands in XIO-SPI or when using DIO-SPI, DQ[1:0] are I/O. DQ[3:2] are not

used.

When using quad commands in XIO-SPI or when using QIO-SPI, DQ[3:0] are I/O.

Supply Core and I/O power supply.

256Mb, 1.8V Multiple I/O Serial Flash Memory

Signal Descriptions

CCMTD-1725822587-3458

mt25q_qljs_U_256_ABA_xxT.pdf - Rev. K 07/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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